Texas Instruments Corporation

Christopher Lyle Borst

Deepak Arabagatte Ramappa

Mona M Eissa

Ting Yiu Tsui

Alwin J Tsao

Noel M Russell

Bobby D Strong

Andrew Tae Kim

Matthew W Losey

Methods () are presented for protecting copper structures () from corrosion in the fabrication of semiconductor devices (), wherein a thin semiconductor or copper-semiconductor alloy corrosion protection layer () is formed on an exposed surface () of a copper structure () prior to performance of metrology operations (), so as to inhibit corrosion of the copper structure (). All or a portion of the corrosion protection layer () is then removed () in forming an opening in an overlying dielectric () in a subsequent interconnect layer.

Post-polish treatment for inhibiting copper corrosion

A method of CMP polishing of a semiconductor wafer is described that includes using a polishing pad on a platen/table with the polishing pad including a sub-pad containing pockets of magnetorheological fluid. The stiffness of the sub-pad is controlled by selectively applying a magnetic field at selective pockets containing magnetorheological fluid to change the viscosity of the magnetorheological fluid. The changing stiffness increases the polishing rate of the pad in the areas of the magnetic field.

Real-time polishing pad stiffness-control using magnetically controllable fluid

Semiconductor devices and manufacturing methods therefor are disclosed, in which conductive fill structures are provided in fill regions in an interconnect wiring layer between conductive wiring structures to facilitate planarization uniformity during metalization processing. One approach employs fill structures of varying sizes where smaller fill structures are formed near wiring regions having high aspect ratio wiring structures and larger fill structures are located near wiring regions with lower aspect ratio wiring structures. Another approach provides fill structures with varying amounts of openings, with fill structures having few or no openings being provided near low aspect ratio wiring structures and fill structures having more openings being located near higher aspect ratio wiring structures.

Methods and semiconductor devices with wiring layer fill structures to improve planarization uniformity

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Plano, TX, United States of America

Christopher Lyle Borst