Lsi Logic Corporation

Western Digital Ventures, Inc.

Other

Lsi Corporation

Suvolta, Inc.

Blackridge Technology Holdings, Inc.

Apple Inc.

Western Digital Technologies, Inc.

Christopher Luis Hamlin

Michael K Eneboe

James S Koford

John William Hayes

Andrew D Hospodor

Ashok K Kapoor

Madhukar B Vora

Payman Zarkesh-Ha

Charles Andrew Gram

At least a portion of a software image may be executed on a first instance of a computing platform. A first sequence of multi-dimensional execution states may be measured that the first instance of the computing platform passes through when executing the portion of the software image. The portion of the software image may then be executed on a second instance of the computing platform. A second sequence of multi-dimensional execution states may be measured that the second instance of the computing platform passes through when executing the portion of the software image. The integrity of the second instance of the computing platform may be verified with respect to the first instance of the computing platform by comparing the first sequence of multi-dimensional execution states with the second sequence of multi-dimensional execution states.

Verifying the integrity of a computing platform

Systems and techniques are described for verifying the integrity of a computing platform. Specifically, a software image can be generated that, when executed at a computing platform, verifies integrity of the computing platform. Next, the software image can be sent to the computing platform. The computing platform can execute the software image, thereby enabling the verification of the integrity of the computing platform.

Technique and systems for detecting network intrusion are described. Each device in a plurality of devices in the network can generate an integrity report by: (1) measuring a first set of execution parameter values during an execution of a portion of a software image at the device, (2) comparing the first set of execution parameter values with a second set of execution parameter values associated with executing the portion of the software image at a secure instance of the device, and (3) generating the integrity report based on said comparing. Next, the integrity reports can be collected, and network intrusions can be detected based on the integrity reports by using statistical and pattern recognition techniques including but not limited to neural nets implementing crossover and backpropagation, and classifiers including but not limited to cluster analysis, correlation and regression, factor analysis.

Using integrity reports to detect network instrusion

Circuitry to facilitate verification of the integrity of a target instance of a computing platform is described. Specifically, a processor can include circuitry to measure execution parameter values during an execution of a portion of a software image, wherein the execution parameter values represent a sequence of execution states that the target instance of the computing platform passes through while executing the portion of the software image. During operation, a software image can be generated that, when executed at the target instance of the computing platform, verifies integrity of the computing platform. Next, the software image can be sent to the target instance of the computing platform. The processor at the target instance of the computing platform can execute the software image, thereby enabling the verification of the integrity of the target instance of the computing platform.

Circuitry to facilitate verifying the integrity of a computing platform

A mechanism to activate an original object (S) so that statistical objects (S) generated from the original object can be recognized using statistical object identification is disclosed. An object activation agent () with a clock () and at least one original object (S) communicates the original object (S) and time from the clock () to an object activation service (). The object activation service () provides and communicates keying information () and expiration criterion () for at least one of said original objects (S) back to the object activation agent ().

Method for statistical object indentification

The present invention enables an enterprise to move from an implicitly trusted resource pool to an explicitly authenticated resource pool. Trust information is generally conveyed whenever a new resource is added to the pool and trust information is revoked when a resource is removed from the pool or is unable to provide its advertised resources. The dynamic, event driven conveyance of trust information is particularly important in highly virtualized environments where virtual resources are dynamically scaled up and down in response to resource demand.

Method for directing requests to trusted resources

The present invention provides a mechanism to communicate an original object (S) without requiring the sending of the complete original object. A representative of the original object (S), a statistical object (S), is generated by one entity and is communicated to a second entity. The second entity receives the statistical object (S), and identifies it as being generated from an original object (S). If the second entity is unable to unambiguously identify the statistical object (S), the second entity records the partial identity progress and associated communications characteristics information (). The amount of information communicated during this process is much smaller than the original object (S), greatly improving the speed and efficiency of communicating an original object (S).

Method for statistical object identification

The present invention is directed to a distributed architecture of an information handling system, including a buried nucleus inaccessible for inspection without heroic means while the buried nucleus is in operation, and a trusted authority for generating a secure protocol. The secure protocol controls the operation of the buried nucleus.

3-prong security/reliability/real-time distributed architecture of information handling system

A method for modeling a circuit includes generating a circuit model based on a netlist that defines a plurality of connections between a plurality of circuit elements. The circuit model includes a model of one or more of the circuit elements. The method further includes determining a wire width associated with at least a selected connection based, at least in part, on design rules associated with the netlist. Additionally, the method includes determining a wire thickness associated with the selected connection based, at least in part, on a signal delay associated with the wire thickness. Furthermore, the method also includes routing the selected connection in the circuit model using a wire having a width substantially equal to the wire width calculated for the connection and a thickness equal to the wire thickness calculated for the connection and storing the circuit model in an electronic storage media.

System and method for routing connections with improved interconnect thickness

A circuit can include an amplifier having at least a first junction field effect transistor (JFET) of a first conductivity type with a source coupled to a first power supply node, and a drain coupled to an amplifier output node. A first variable bias circuit can be coupled between the drain and at least one gate of the first JFET. The first variable bias circuit can alter a direct current (DC) bias to the first JFET according a potential at the amplifier output node. A first bias impedance can be coupled between the drain of the first JFET and a second power supply node. The circuit can also include a non-linear transmission line (NLTL) coupled between the amplifier output and a gate of the first JFET. The NLTL being configured to propagate an electrical soliton.

Circuit and method for generating electrical solutions with junction field effect transistors

A method for modeling a circuit includes receiving a netlist that defines a plurality of connections between a plurality of circuit elements and identifying a subset of the connections. The method also includes routing the identified connections with a first group of wires having a first wire width and routing at least a portion of the remaining connections with a second wire width. The second wire width is smaller than the first wire width. The method further includes replacing the first group of wires with a third group of wires having the second wire width.

System and method for routing connections

The present invention provides a comprehensive design environment defining a system architecture and methodology that may integrate interconnects, cores, ePLC, re-configurable processors and software into a manageable and predictable system designs that achieve on-time system IC design results meeting desired specifications and budgets. For example, an interscalable interconnect maybe provided that is scalable and isochronous capable. Additionally, an abstract language may be provided to be able to describe interconnecting core functions. Further, a self-programmable chip may be provided that, upon receiving a construct, it could program itself to achieve the desired functionality, such as through the use of on-chip knowledge and the like.

Growing community of inventors

Los Gatos, CA, United States of America

Christopher Luis Hamlin