Fairchild Semiconductor Corporation

Christopher Lawrence Rexer

Joseph Andrew Yedinak

Chongman Yun

Richard L Woodin

Hamza Yilmaz

Praveen Muraleedharan Shenoy

Jaegil Lee

Kwanghoon Oh

Steven Paul Sapp

Daniel S Calafut

Paul Thorup

Ritu Sodhi

Praveen Muralheedaran Shenoy

Christopher Boguslaw Kocon

Dean E Probst

James N Pan

Gary M Dolny

Becky Losee

Robert Herrick

Mark L Rinehimer

Michael D Gruenhagen

Fred Session

Dwayne S Reichl

Dan Kinzer

Carl Anthony Witt

Hocheol Jang

Rohit Dikshit

Tracie Petersen

Joseph Shovlin

In one general aspect, a power device can include an active region having a plurality of pillars of a first conductivity type alternately arranged with a plurality of pillars of a second conductivity type. The power device can include a termination region surrounding at least a portion of the active region and can have a plurality of pillars of the first conductivity type alternately arranged with a plurality of pillars of the second conductivity type. Each of the plurality of pillars of the first conductivity type in the active region and the termination region can be defined by a trench. The power device can include an enrichment region at a bottom portion of one of the plurality of pillars of the first conductivity type in the active region.

Superjunction structures for power devices

In one general aspect, a power device includes an active region having a plurality of pillars of a first conductivity type alternately arranged with a plurality of pillars of a second conductivity type where the plurality of pillars of the second conductivity type in the active region each have substantially the same width. The power device includes a termination region surrounding at least a portion of the active region and having a plurality of pillars of the first conductivity type alternately arranged with a plurality of pillars of the second conductivity type where the plurality of pillars of the second conductivity type in the active region each have substantially the same width and are smaller than each width of the pillars of the second conductivity type in the termination region. The power device includes a transition region disposed between the active region and the termination region.

A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

Superjunction structures for power devices and methods of manufacture

A semiconductor structure includes a monolithically integrated trench FET and Schottky diode. The semiconductor structure further includes a plurality of trenches extending into a semiconductor region. A stack of gate and shield electrodes are disposed in each trench. Body regions extend over the semiconductor region between adjacent trenches, with a source region extending over each body region. A recess having tapered edges extends between every two adjacent trenches from upper corners of the two adjacent trenches through the body region and terminating in the semiconductor region below the body region. An interconnect layer extends into each recess to electrically contact tapered sidewalls of the source regions and the body regions, and to contact the semiconductor region along a bottom of each recess to form a Schottky contact therebetween.

High density FET with integrated Schottky

In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (FET) and Schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench. The source region can have a substantially triangular shape, and a contact opening extending into the semiconductor region between the first gate trench and the second gate trench. The structure can include a conductor layer disposed in the contact opening to electrically contact the source region along at least a portion of a slanted sidewall of the source region, and the semiconductor region along a bottom portion of the contact opening. The conductor layer can form a Schottky contact with the semiconductor region.

Field effect transistor and schottky diode structures

A semiconductor structure which includes a shielded gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A shield dielectric is formed extending along at least lower sidewalls of each trench. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD. A shield electrode is formed in a bottom portion of each trench. A gate electrode is formed over the shield electrode in each trench.

Structure related to a thick bottom dielectric (TBD) for trench-gate devices

This document discusses, among other things, a semiconductor device including a first metal layer coupled to a source region and a second metal layer coupled to a gate structure, wherein at least a portion of the first and second metal layers overlap vertically.

Double layer metal (DLM) power MOSFET

A semiconductor device includes a drift region, a well region extending above the drift region, an active trench including sidewalls and a bottom, the active trench extending through the well region and into the drift region and having at least portions of its sidewalls and bottom lined with dielectric material. The device further includes a shield disposed within the active trench and separated from the sidewalls of the active trench by the dielectric material, a gate disposed within the active trench above the first shield and separated therefrom by inter-electrode dielectric material, and source regions formed in the well region adjacent the active trench. The gate is separated from the sidewalls of the active trench by the dielectric material. The shield and the gate are made of materials having different work functions.

Trench power MOSFET with reduced on-resistance

An electrical device on a single semiconductor substrate includes: an open base vertical PNP transistor placed in parallel with a wide bandgap, high voltage diode wherein the PNP transistor has a P doped collector region, an N-doped base layer, an N doped buffer layer, and a P doped emitter layer.

Wide bandgap device in parallel with a device that has a lower avalanche breakdown voltage and a higher forward voltage drop than the wide bandgap device

A wide bandgap silicon carbide device has an avalanche control structure formed in an epitaxial layer of a first conductivity type above a substrate that is connected to a first electrode of the device. A first region of a second conductivity type is in the upper surface of the epitaxial layer with a connection to a second electrode of the device. A second region of the first conductivity type lies below the first region and has a dopant concentration greater than the dopant concentration in the epitaxial layer.

Rugged semiconductor device architecture

A method and device for protecting wide bandgap devices from failing during suppression of voltage transients. An improvement in avalanche capability is achieved by placing one or more diodes, or a PNP transistor, across the blocking junction of the wide bandgap device.

A wide bandgap device in parallel with a device having a lower avalanche breakdown voltage and a higher forward voltage drop than the wide bandgap device.

A monolithically integrated field effect transistor and Schottky diode includes gate trenches extending into a semiconductor region. Source regions having a substantially triangular shape flank each side of the gate trenches. A contact opening extends into the semiconductor region between adjacent gate trenches. A conductor layer fills the contact opening to electrically contact: (a) the source regions along at least a portion of a slanted sidewall of each source region, and (b) the semiconductor region along a bottom portion of the contact opening, wherein the conductor layer forms a Schottky contact with the semiconductor region.

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Mountain Top, PA, United States of America

Christopher Lawrence Rexer