Apple Inc.

Advanced Micro Devices Corporation

Ati Technologies Ulc

Christopher L Spencer

Jeffrey T Brady

Michael Mantor

Terence M Potter

Ralph Clay Taylor

Dimitri Tan

Andrew Evan Gruber

Daniel Wong

Karl D Mann

Brian Laird Sumner

Daniel Clifton

Mark D Earl

Dinesh D Kuwar

Yun-Xiao Zou

In various embodiments, a resource allocation management circuit may allocate a plurality of different types of hardware resources (e.g., different types of registers) to a plurality of threads. The different types of hardware resources may correspond to a plurality of hardware resource allocation circuits. The resource allocation management circuit may track allocation of the hardware resources to the threads using state identification values of the threads. In response to determining that fewer than a respective requested number of one or more types of the hardware resources are available, the resource allocation management circuit may identify one or more threads for deallocation. As a result, the hardware resource allocation system may allocate hardware resources to threads more efficiently (e.g., may deallocate hardware resources allocated to fewer threads), as compared to a hardware resource allocation system that does not track allocation of hardware resources to threads using state identification values.

Hardware resource allocation system for allocating resources to threads

Techniques are disclosed relating to memory allocation in a graphics shader. In some embodiments, a memory for storing input data for operations by the shader is shared for multiple different types of tasks (e.g., pixel shading tasks and compute tasks). In some embodiments, a graphics device is configured to separately process different portions (e.g., tiles) of a frame of graphics data. In some embodiments, the graphics device is configured to dynamically adjust the number of frame portions processed in parallel based on allocation information, where the allocation information is determined based on requests for other types of tasks. This may prevent pixel shading tasks from stalling other tasks for extended periods and may allow dynamic adjustments memory allocation mid-render.

Memory allocation techniques for graphics shader

Techniques are disclosed relating to rendering graphics objects that require shader operations to determine visibility. In some embodiments, a graphics unit is configured to process feedback objects, which may require shading to determine whether they are visible relative to previously-processed objects, out of draw order. For example, in embodiments where a buffer is used to store fragment data for deferred rendering, the graphics unit may bypass the buffer and shade feedback objects ahead of earlier non-feedback objects whose fragment data is stored in the buffer. This may allow a determination of whether to remove occluded non-feedback fragment data from the buffer, which may reduce graphics overdraw. In disclosed two-pass techniques, data for feedback objects is first allowed to bypass the buffer for visibility shading, but is then stored in the buffer for a second pass to perform fragment shading to actually determine pixel attributes, which may further reduce overdraw.

Punch-through techniques for graphics processing

A method and apparatus for additive range reduction are disclosed. A constant may be pre-stored in a look-up table (LUT), and at least one section of the constant may be retrieved from the LUT for generating a product of an input argument and the constant such that a precision of the product may be controlled in any granularity. For a trigonometric function, 2/&#x3c0; is stored in the LUT, and at least one section of 2/&#x3c0; may be retrieved from the LUT. The argument is multiplied with the retrieved sections of 2/&#x3c0;. The retrieved sections are determined to correctly generate the two least significant bits (LSBs) of an integer portion and a scalable number of most significant bits of the multiplication result. An output of the trigonometric function is generated for the argument with a fractional portion of the multiplication result based on two LSBs of the integer portion of the multiplication result.

Method and apparatus for additive range reduction

Disclosed herein is a processing unit configured to process video data, and applications thereof. In an embodiment, the processing unit includes a buffer and an execution unit. The buffer is configured to store a data word, wherein the data word comprises a plurality of bytes of video data. The execution unit is configured to execute a single instruction to (i) shift bytes of video data contained in the data word to align a desired byte of video data and (ii) process the desired byte of the video data to provide processed video data.

Video instruction processing of desired bytes in multi-byte buffers by shifting to matching byte location

Systems and methods for multi-precision computation are disclosed. One embodiment of the present invention includes a plurality of multiply-add units (MADDs) configured to perform one or more single precision operations and an arrangement generator to generate one or more mantissa arrangements using a plurality of double precision numbers. Each MADD is configured to receive and load said mantissa arrangements from the arrangement generator. The MADDs compute a result of a multi-precision computation using the mantissa arrangements. In an embodiment, the MADDs are configured to simultaneously perform operations that include, single precision operations, double-precision additions and double-precision multiply and additions.

Growing community of inventors

Chuluota, FL, United States of America

Christopher L Spencer