Advanced Micro Devices Corporation

Other

Christopher L Reeve

Michael John Bedy

Robert A Gottlieb

William Frederick Mann, Iii

James B Rothnie

Linda Q Lee

Jacklin Kotikian

Timothy G Peters

Tani Shavit

A method and apparatus for scheduling instructions of a shader program for a graphics processing unit (GPU) with a fixed number of registers. The method and apparatus include computing, via a processing unit (PU), a liveness-based register usage across all basic blocks in the shader program, computing, via the PU, the range of numbers of waves of a plurality of registers for the shader program, assessing the impact of available post-register allocation optimizations, computing, via the PU, the scoring data based on number of waves of the plurality of registers, and computing, via the PU, the number of waves for execution for the plurality of registers.

System and method for scheduling instructions in a multithread SIMD architecture with a fixed number of registers

An improved parallel processing apparatus and method executes an iterative sequence of instructions by arranging the sequence into subtasks and allocating those subtasks to processors. This division and allocation is conducted in such a manner as to minimize data contention among the processors and to maximize the locality of data to them. The improved apparatus and method have application to a variety of multiprocessor systems, including those which are massively parallel.

System for parallel processing that compiles a filed sequence of

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Boxborough, MA, United States of America

Christopher L Reeve