Lsi Logic Corporation

Nantero, Inc.

Lsi Corporation

Christopher L Neville

Colin D Yates

Randy M Yim

Mario Garza

Ebo H Croffie

Claude Louis Bertin

Thomas Rueckes

Nicholas K Eib

Mitchell Meinhold

Steven L Konsek

Neal Patrick Callan

Philip Eric Jackson

A method of forming an aligned connection between a nanotube layer and a raised feature is disclosed. A substrate having a raised feature has spacers formed next to the side of the raised feature. The spacers are etched until the sidewalls of the raised feature are exposed forming a notched feature at the top of the spacers. A patterned nanotube layer is formed such that the nanotube layer overlies the top of the spacer and contacts a side portion of the raised feature in the notched feature. The nanotube layer is then covered with an insulating layer. Then a top portion of the insulating layer is removed to expose a top portion of the etched feature.

Method of aligning deposited nanotubes onto an etched feature using a spacer

The invention provides a method of performing process window compliant corrections of a design layout. The invention includes an operator performing the following steps: (1) simulating Develop Inspect Critical Dimension (DI CD) at best exposure conditions using the provided original layout pattern; (2) simulating DI CD at predefined boundary exposure conditions using the provided original layout pattern; (3) if the DI CD from step (1) meets the target DI CD definition, and the DI CD from step (2) meets process window specifications, convergence takes place; and (4) modifying the layout pattern and repeating steps (2) through (3) until DI CD from step (2) reaches the specification limit if any portion of step (3) is not achieved.

Process window compliant corrections of design layout

A method and apparatus for improving resolution in photolithography. The method includes steps of mapping a first phase onto a first mask, mapping a second phase onto a second mask, and mapping a trim onto the first mask or second mask (or both). Specifically, the first mask may include Phase1 mapped to 0/180 phase, and the second mask may include Phase2 and trim mapped to 0/180 phase. A set of masks consistent with the foregoing is provided.

Multiple alternating phase shift technology for amplifying resolution

Disclosed is a pupil aperture, and method for making the pupil aperture for use in a photolithography scanner system. The pupil aperture includes a plate having a set of pole apertures that are radially offset from a reference center point of the plate. The plate further includes a horizontal reference line that intersects the reference center point. The horizontal reference line is used to define a target angle that is between about 15 degrees and about 35 degrees from the horizontal reference line. The target angle defines an off-axis location for each of the set of pole apertures. In a specific aspect of this invention, a set ranging between 3 to 9 pole apertures can be defined in the plate, and their offset from the center point can be selected to be between about 0.3 inches and about 0.9 inches.

Off-axis pupil aperture and method for making the same

A test reticle and alignment mark optimization method is provided for determining the optimal alignment mark size for the efficient and accurate alignment of process layers during integrated circuit manufacture. The test reticle includes a number of orthogonally arranged alignment marks of various types and sizes and one or more registration structures. The method involves the steps of determining an initial expected range of alignment mark sizes on the test reticle which are suitable for a particular application; applying the test reticle patter to test wafers; further processing the test wafers; measuring the alignment signals produced by scanning the alignment marks in the initial expected range; quantifying the alignment signal quality; and fitting the quantified alignment signal quality to a statistical model to determine a range of optimal alignment signal dimensions.

Method of using a test reticle to optimize alignment of integrated

Integrated circuit test reticle and alignment mark optimization method

A test reticle and alignment mark optimization method is provided for determining the optimal alignment mark size for the efficient and accurate alignment of process layers during integrated circuit manufacture. The test reticle includes a number of orthogonally arranged alignment marks of various types and sizes and one or more registration structures. The method involves the steps of determining an initial expected range of alignment mark sizes on the test reticle which are suitable for a particular application; applying the test reticle pattern to test wafers; further processing the test wafers; measuring the alignment signals produced by scanning the alignment marks in the initial expected range; quantifying the alignment signal quality; and fitting the quantified alignment signal quality to a statistical model to determine a range of optimal alignment signal dimensions.

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Portland, OR, United States of America

Christopher L Neville