Raytheon Company

Christopher L Fletcher

Andrew G Toth

Michael S Ray

Kenton T Veeder

David J Gulbransen

Jeffrey M Peterson

Frank B Jaworski

William J Hamilton, Jr

Ronald W Berry

Eli E Gordon

Jerry R Cripe

Martins Skele

An imaging system for receiving data from a scene and displaying an image therefrom includes a detector and a display. The detector includes a plurality of detector pixels on a first side of the detector, readout circuitry on an opposing second side of the detector or between the detector and the detector pixels on the first side of the detector, and a plurality of detector vias configured to provide electrical connectivity for the plurality of detector pixels through the detector. The display includes a plurality of display pixels on one side of the display, read in circuitry on an opposing second side of the display or between the display and the display pixels on the first side of the display, and a plurality of display vias configured to provide electrical connectivity for the plurality of display pixels through the display. The read in circuitry is coupled with the readout circuitry.

Integrated detection and display imaging system and method

In one embodiment, a method of preparing detectors for oxide bonding to an integrated chip, e.g., a readout integrated chip, includes providing a wafer having a plurality of detector elements with bumps thereon. A floating oxide layer is formed surrounding each of the bumps at a top portion thereof. An oxide-to-oxide bond is formed between the floating oxide layer and an oxide layer of the integrated chip which is provided in between corresponding bumps of the integrated chip. The oxide-to-oxide bond enables the bumps on the detector elements and the bumps on the integrated chip to be intimately contacted with each other, and removes essentially all mechanical stresses on and between the bumps. In another embodiment, a device has an interconnect interface that includes the oxide-to-oxide bond and an electrical connection between the bumps on the detector elements and the bumps on the integrated chip.

Method of preparing detectors for oxide bonding to readout integrated chips

A unit cell () is disclosed that has an input node for coupling to an output of a detector (D) of electromagnetic radiation, such as IR or visible radiation. The unit cell includes a first capacitor (C) switchably coupled to the input node for receiving a charge signal from the detector, and for integrating the charge signal during a first integration period, as well as a second capacitor (C)switchably coupled to the input node for integrating the charge signal during a second integration period. The unit cell further includes an output multiplexer () for selectively coupling the first capacitor and the second capacitor to an output signal line () during respective charge signal readout periods. In the preferred embodiment a duration of the first integration period is one of greater than or less than the second integration period, and the first integration period is one of non-overlapping or overlapping with the second integration period, and vice versa. The first integration period can be interleaved with the second integration period, or vice versa.

Multi-mode high capacity dual integration direct injection detector input circuit

The present invention concerns, in part, a method for fabricating a silicon PIN detector component wherein three handle wafers are bonded to the wafer at varying points in the fabrication process. The utilization of three handle wafers during fabrication significantly ease handling concerns associated with what would otherwise be a relatively thin and fragile wafer, providing a stable and strong base for supporting those portions of the wafer that will constitute the PIN detector component. In a variant of the present invention, the third handle wafer comprises an optical element transparent in the wavelength of interest.

Method for fabricating a high performance PIN focal plane structure using three handle wafers

A PIN detector device () is fabricated on a substrate (). The substrate () includes a handle wafer portion (), an implanted oxide layer (), a backside contact layer () and an active wafer portion (). The substrate () serves as a foundation to increase stability and facilitate handling during fabrication of electrical circuitry () on a surface of the active wafer portion (). After the electrical circuitry fabrication processing is substantially complete, the handle wafer portion () and implanted oxide layer () are removed to expose the implanted backside contact layer ().

Pin detector apparatus and method of fabrication

A low power delta-sigma analog to digital converterfor converting current mode signals without an amplifier includes an integration capacitora comparatorand a first switchin parallel with one another and coupled to an integration nodeA FETand the first switch are disposed in series between a dump capacitorand the integration node. A second switchoperates to discharge the dump capacitor, and an output of the comparator controls both switches in opposition. Preferably, no op-amps are included in the circuit, and current is supplied by an imaging componentIn a first comparator state, the first capacitor charges, the first switch is open and the second switch is closed, and the dump capacitor discharges. In a comparator second state, the first switch is closed and the second switch is open, and the integration capacitor transfers a fixed amount of charge into the dump capacitor through an injection FET operating in saturation.

Low power current input delta-sigma ADC using injection FET reference

A monolithic microelectronic array structure includes a microelectronic integrated circuit array having a first plurality of microelectronic integrated circuit elements each deposited on a front side of a substrate. The substrates are physically discontinuous so that each substrate comprises a substrate island which is physically separated from the other substrate islands. The monolithic microelectronic array structure optionally includes a first plurality of input/output elements with a respective input/output element associated with and directly connected to each of the microelectronic integrated circuit elements, and a second plurality of electrically conductive interconnects extending between the microelectronic integrated circuit elements of adjacent substrate islands. The monolithic microelectronic array structure may be planar, or it may be curved.

Monolithic microelectronic array structure having substrate islands and its fabrication

A method for forming very large scale integrated circuit devices employs a reticle having plural discrete image fields which may be respectively blocked off and exposed to form patterns on an integrated circuit wafer substrate. The division of the circuit pattern to be imaged into separate image fields is based on repeatable horizontal, vertical and two dimensional structures in the overall circuit pattern of the integrated circuit. By repeatedly exposing image fields corresponding to repeatable structures, the size of the integrated circuit device may be scaled without requiring similar scaling of the reticle itself. Efficient exposure of an entire wafer may be provided by having image fields including circuit patterns which include the scribe lanes which separate the integrated circuits on the wafer to be imaged.

Growing community of inventors

Santa Barbara, CA, United States of America

Christopher L Fletcher