Infineon Technologies Ag

Qimonda Ag

Qimonda North America Corporation

Christopher Kunce

Alan Daniel

Torsten Partsch

Benjamin Louis Heilmann

Biju Velayudhan

Ding-Cheung Yu

In one embodiment, a memory device comprises a semiconductor substrate, a first set of memory banks disposed on the semiconductor substrate and a second set of memory banks disposed on the semiconductor substrate. Each memory bank of the second set is split into a plurality of memory bank segments physically separated from each other and from the first set of memory banks. Each memory bank segment is arranged adjacent to, and occupies less area than, one of the memory banks of the first set.

Multi-bank memory device method and apparatus

In one embodiment, a memory device comprises a plurality of banks and a refresh controller. Each bank is logically divisible into at least two different sections of memory cells during a refresh operation. The refresh controller successively identifies each of the sections using a first portion of a row address and addresses a row of memory cells included in each of the sections using a second portion of the row address. The refresh controller also successively selects two or more different groups of the banks during different time intervals each time a different one of the sections is identified. The refresh controller refreshes the addressed row of memory cells included in the most recently identified section of each bank for the most recently selected group of banks.

Memory device refresh method and apparatus

An integrated circuit includes a core memory array and a test mode compression circuit. The test mode compression circuit receives test mode data from the core memory array. A multiplexer receives read data from the core memory array and test mode data from the test mode compression circuit. The multiplexer receives a test mode compression signal and selectively transfers one of the read data and the test mode data dependent at least in part upon the test mode compression signal.

Method and apparatus for providing adjustable latency for test mode compression

A system of multiplexed data lines in a DRAM integrated circuit includes a switching circuit having two switching states. In one switching state, the data lines connect to a first configuration of data paths as would occur in a typical DRAM integrated circuit. A limited number of spare column select lines are available to repair defective column select lines in the first configuration. In another switching state, the data lines connect to a second configuration of the data paths, doubling the number of spare column select lines available to repair a defective column select line.

Growing community of inventors

Wake Forest, NC, United States of America

Christopher Kunce