Knowles Electronics, Inc.

National Semiconductor Corporation

Christopher Konrad Wolf

Frederic Denis Raynal

Niel David Warren

Ygal Arbel

Himanshu A Sanghavi

Erick Alvarado

Malav Shah

Sean Mahnken

Systems and methods are disclosed for an audio processor that includes a clock detection circuit and a clock bypass circuit. According to various embodiments, the clock detection circuit can check and indicate the status of a main clock and upon detection of a loss of the main clock, the clock bypass circuit can switch the source of the main clock to an alternate source such as an on chip oscillator allowing the system to gracefully recover from the clock loss event.

Clock detection and automatic PLL output bypass switching for an audio processor

Disclosed herein are related to a system and a method for synchronizing signal processing on audio channels. In one aspect, a system includes processors, each including an audio data input configured to receive audio data from multiple audio sources. In one aspect, each processor includes audio channels coupled to the audio data input, where each audio channel includes a corresponding processing chain configured to convert a sample rate of audio data from a corresponding audio source. Each processor may include a synchronization pulse generator configured to generate a corresponding synchronization pulse for each processing chain in response to a trigger pulse. The synchronization pulse generator may include a counter configured to generate an output having a phase based on a programmable initial condition of the counter, where the synchronization pulse for each processing chain is based on the counter output and a phase register value of the corresponding processing chain.

Synchronization of multiple audio processing chains

A multi-core audio processor includes an audio fabric block configured to organize data received from a plurality of audio interfaces into streams for processing by a plurality of digital signal processing cores. The plurality of digital signal processing cores include a single sample processing core and a frame processing core. The multi-core audio processor also includes a pool of undedicated random access memory (RAM) and a main controller configured to dynamically allocate memory resources from the pool of undedicated RAM amongst one or more of the plurality of digital signal processing cores.

Multi-core audio processor with flexible memory allocation

A method in a transducer assembly having an external-device interface coupled to a communication protocol interface of the transducer assembly. The transducer assembly is configured to convert an input signal having one physical form to an output signal having a different physical form. At least two electrical signals are received on corresponding contacts of the external-device interface of the transducer assembly. A characteristic of at least one of the electrical signals is determined by evaluating a logic transition of the signal. A unique identity assigned to the transducer assembly is determined based on the characteristic.

Transducer assemblies and methods

A system () for decoding a data stream allocated into data packets contains a control unit (), a stream demultiplexer (), audio and video decoders (and), a memory management unit (), and audio and video input and output buffers. Upon demultiplexing and depacketizing the data packets without interrupting the control unit, the demultiplexer sends encoded audio and video data to the audio and video input buffers. Video messages dealing with video timing information and identifying where encoded video data is stored in the video input buffer are furnished by the demultiplexer for use by the control unit. Utilizing corresponding video instructions provided from the control unit, the video decoder decodes encoded video data to produce decoded video data supplied to the video output buffer. The audio decoder decodes encoded audio data to produce decoded audio data supplied to the audio output buffer. The memory management unit controls transfer of decoded audio data to and from the audio output buffer.

System and method for decoding audio/video data such as DVD or/and DVB data

An improved synchronization circuit has a numerically controlled oscillator (NCO) having an accumulator, a number line, and feedback line fed back from the accumulator output. The accumulator repeatedly adds the number represented on the number line and the number represented on the feedback line and feedbacks the result to the accumulator. The result rolls over to zero as would an odometer when it reaches a maximum value. When the number represented on number input is properly selected by, for example, a microprocessor, a data stream representing the most significant bit of the result has jitter. The synchronization circuit also has a phase-locked loop (PLL) configured to receive the data stream of the most significant bit. The frequency of the most significant bit stream and the frequency of the jitter on that bit stream are controlled by the number at the number input. The number is chosen to maximize the jitter frequency and thus maximize jitter attenuation through the PLL.

NCO based frequency synthesizer with jitter modulation

The present invention provides a method and apparatus for providing video output phase control in a decoder. In particular, the present invention provides a decoder that precisely aligns output of video display data with a time stamp associated with the video display data and thereby allows for efficient usage of compressed video buffer memory in the decoder. In one embodiment, the decoder includes a video output processor for displaying video data and a timer connected to the video output processor for providing video output phase control. A method is also provided for providing video output phase control in the decoder.

Growing community of inventors

San Jose, CA, United States of America

Christopher Konrad Wolf