Qualcomm Incorporated

Christopher Kong Yee Chun

Lalan Jee Mishra

Richard Dominic Wietfeldt

Mohit Kishore Prasad

Chris M Rosolowski

Hee Jun Park

Chiew-Guan Tan

Steven S Thomson

Haw-Jing Lo

Michael Drop

Ali Iranli

Tao Xue

Sriharsha Chakka

Vinodh Ramesh Cuppu

Dexter Tamio Chun

Moinul H Khan

Todd Robert Sutton

Radu Pitigoi-Aron

Anand Srinivasan

Vishal Agarwal

Matthew Levi Severson

Helena Deirdre O'Shea

Shadi Hawawini

Wolfgang Roethig

Wilson Jianbo Chen

Dipti Ranjan Pal

Umesh Srikantiah

Joshua Stubbs

Gordon P Lee

Naveen Kumar Narala

Srivathsa Sridhara

ZhenQi Chen

Yuancheng Christopher Pan

Taewoo Kwak

John Milford Fletcher

Navdeep Mer

Scott Davenport

Kumar Kanti Ghosh

Saurabh Gorecha

Naresh Kumar Sharma

Pravin Kumar

Chandan Agarwalla

Chris Rosolowski

Moinul H Kahn

Nilanjan Banerjee

Sreenivasan Jouly Jothiram

Jai Babu Mahankud

Michael J Drop

Various embodiments include methods for implementing command transactions on a two-wire bus system of a computing device, and devices for implementing the methods. Embodiments may include receiving, by a two-wire interface of a host device, an abort signal via a two-wire bus, and transmitting, by the two-wire interface of the host device, an end signal via the two-wire bus in response to receiving the abort signal. Embodiments may further include transmitting, by a two-wire interface of a bus owner device, commands via the two-wire bus prior to receiving the end signal, receiving, by the two-wire interface of the bus owner device, the end signal via the two-wire bus; and terminating, by the two-wire interface of the bus owner device, transmitting commands in response to receiving the end signal. Some embodiments may include transmitting the commands following an instance of bus arbitration and prior to a subsequent instance of bus arbitration.

Multi-command transactions

Various embodiments include systems and methods for balancing battery cycles of paired earbuds. A processor in an earbud charging case may receive battery level information from a first earbud operating in a deep sleep mode, determine a battery differential index (BDI) value, and send an instruction message to the first earbud indicating the first earbud should switch roles with a second earbud. An earbud may start a timer upon beginning to operate in a dormant mode, transition from operating in the dormant mode to operating in a non-dormant mode in response to expiration of the timer, send a message to a paired earbud indicating that the earbud has transitioned, and receive a message from the paired earbud indicating that the earbud should switch from operating in the dormant mode to operating in the deep sleep mode and periodically broadcasting an advertisement.

Power efficient always-on low energy Bluetooth advertising

Systems and methods for bus clock line handover are disclosed. In one aspect, a clock line in a bus is driven continuously during bus handover without having contentious or contradictory drive signals being provided. After arbitration, an original bus master will drive the clock line to a predetermined value until detecting a state change on a data line. An incoming bus master will begin driving the clock line to the predetermined value and then drive a state change on the data line. This state change is the state change detected by the original bus master that causes the original bus master to stop driving the clock line.

Bus clock line handover systems and methods

Dynamic power supply voltage adjustment in a computing device may involve two stages. In a first stage, a first method for adjusting a power supply voltage may be disabled. While the first method remains disabled, a request to adjust the power supply voltage from an initial value to a target value using a second method may be received. The second method may be initiated in response to the request if a time interval has elapsed since a previous request to adjust the power supply voltage. In a second stage, the first method may be enabled when it has been determined that the power supply voltage has reached the target value.

Two-stage dynamic power supply voltage adjustment

Expanded function datagrams in a system power management interface (SPMI) system allow a slave to use an expanded function datagram to address a larger number of masters (e.g., more than four) associated with the SPMI system. Furthermore, addressing may allow for a datagram to be broadcast to multiple masters concurrently. Still further, by signaling that the master addressing is other than the standard SPMI format, the nature of the address and payload of a datagram may be varied to handle larger volumes of data than the SPMI standard normally allows.

Integrated circuit

Various embodiments of methods and systems for a modem-directed application processor boot flow in a portable computing device ('PCD') are disclosed. An exemplary method includes an application processor that transitions into an idle state, such as a WFI state, for durations of time during a boot sequence that coincide with processing by a DMA engine and/or crypto engine. That is, the application processor may 'sleep' while the DMA engine and/or crypto engine process workloads in response to instructions they received from the application processor.

System and method for modem-directed application processor boot flow

Systems, methods, and computer programs are provided for controlling power in a computing device. One embodiment is a system comprising a plurality of power rails coupled to one or more computing device components. Each power rail has a primary power supply for producing current at a corresponding requested voltage. The system further comprises a shared secondary power supply selectively coupled to the plurality of power rails for providing a current increase. A controller selects one of the plurality of power rails to receive the current increase. The controller generates a control signal to electrically couple the shared secondary power supply to the selected power rail to receive the current increase.

Peak current support for a power rail system via a shared secondary power supply

Systems, methods, and apparatus for communicating datagrams over a serial communication link are provided. A transmitting device generates an address field in a datagram, sets a value of at least one bit in the address field to indicate a number of bytes of data associated with a data frame of the datagram, generates the data frame in the datagram, the data frame including the number of bytes of data, and sends the datagram to a receiving device. A receiving device receives a datagram from a transmitting device, decodes an address field of the datagram to detect a number of bytes of data included in a data frame of the datagram based on a value of at least one bit in the address field, and decodes the data frame to recover the detected number of bytes of data.

Slave master-write/read datagram payload extension

Systems, methods, and apparatus for data communication are provided. A method performed by a bus master includes terminating transmission of a first datagram by signaling a first bus park cycle on a serial bus, causing a driver to enter a high-impedance state, opening an interrupt window by providing a first edge in a clock signal transmitted on a second line of the serial bus, closing the interrupt window by providing a second edge in the clock signal, signaling a second bus park cycle on the serial bus, initiating an arbitration process when an interrupt was received on the first line of the serial bus while the interrupt window was open, and initiating a transmission of a second datagram when an interrupt was not received on the first line of the serial bus while the interrupt window was open.

Asynchronous interrupt with synchronous polling and inhibit options on an RFFE bus

Systems, methods, and apparatus for communicating datagrams over a serial communication link are provided. A receiving device captures a sending device address during bus arbitration and receives a datagram subsequent to the bus arbitration. The datagram includes at least a register address and a payload. The receiving device obtains an address region specific to the sending device within a register space of the receiving device based on the captured sending device address and the register address included in the datagram and writes the payload of the datagram to the register space according to the obtained address region.

Bus communication enhancement based on identification capture during bus arbitration

Systems, methods, and apparatus for improving end-to-end timing closure of a serial bus are described. An apparatus is coupled to a serial bus through an interface circuit and has a clock generator that provides a first clock signal, a delay circuit that is adapted to generate a second clock signal by delaying the first clock signal, and a controller that is configured to cause the interface circuit to use an edge of the first clock signal to initiate transmission of a first data bit over the serial bus during a write operation, delay the first clock signal to obtain a second clock signal, and cause the interface circuit to use an edge of the second clock signal to capture a second data bit from the serial bus during a read operation. The edge of the second clock signal is delayed with respect to the edge of the first clock signal.

Dynamic optimal data sampling time on a multi-drop bus

An integrated circuit includes a processor to monitor a communication interface arbitration sequence on a system bus, determine, based on the monitored arbitration sequence, a master or slave identifier that is sending a transaction on the system bus, and process the transaction based on the determined master or slave identifier that is sending the transaction.

Communication interface transaction security

Systems and methods are disclosed method for operating a serial interconnect of a computer system in a time deterministic manner. An exemplary method comprises that a command to be sent over the serial interconnect in a transaction is to be executed at a specific time. A delay period for the command to be sent from a master of the computer system to a slave of the computer system via the serial bus is determined, where the delay period determined based on a length of an arbitration phase of the transaction. The command is then sent to the slave of the computer system via the serial bus after the delay period.

System and method for deterministic transactions on a serial bus

Systems, methods, and apparatus for communication virtualized general-purpose input/output signals over a serial communication link A method performed at a transmitting device coupled to a communication link includes configuring general-purpose input/output (GPIO) state from a plurality of sources into a virtual general-purpose input/output word, identifying one or more destinations for the first GPIO word based on a mapping of the GPIO state to one or more devices coupled to a serial bus, and transmitting the first GPIO word to each destination.

Multi-port multi-sideband-GPIO consolidation technique over a multi-drop serial bus

Growing community of inventors

Austin, TX, United States of America

Christopher Kong Yee Chun