Motorola Corporation

Freescale Semiconductor,inc.

Qualcomm Incorporated

Motorla, Inc.

Christopher K Chun

Michael S Lebby

Shun-Meen Kuo

Davis H Hartman

Daniel B Schwartz

Melissa Denvir

Stephen G Shook

Cary D Perttunen

Barbara M Foley

Gary F Witting

Gayathri Bhagavatheeswaran

Ray D Sundstrom

Kent W Hansen

Earnest J Johnson

George Edward Charles

Michael Priel

William L Reber

Jon James Anderson

Donald E Ackley

Todd Robert Sutton

Christopher Patrick

John J Vaglica

Charbel Khawand

David Jeffery Hayes

Peter J Zdebel

Gordon P Lee

Carl R Ryan

Bhoodev Kumar

Cor Voorwinden

Dale Brian Halling

Eric Ian Mikuteit

Milind P Padhye

Amy Derbyshire

Mieu Van Vu

Jianping Tao

David Galloway

Arthur M Goldberg

Hong Tian

Kurt K Sakamoto

Matthew Muh

Douglas P Fayden

P Lee Gordon

An electrical current ('EC') manager module may assign a plurality of hardware elements of the PCD to one of two groups. The EC manager module may monitor individual electrical current levels of one of the groups as well as calculate an instantaneous electrical current level for the PCD based on a current charge status for the PCD. The EC manager module may then adjust operation of at least one hardware element to keep operation of the PCD below the calculated instantaneous electrical current level for the PCD. The EC manager module may estimate an electrical current level for one of the groups based on requests issued to hardware elements. The EC manager module may also compare the calculated instantaneous electrical current level to the monitored electrical current level. The calculated instantaneous electrical current level may be compared to minimum current levels listed in a table.

System and method for managing electrical current in a portable computing device

A method for media access control, the method includes generating at least one media access grant in response to at least one media access request. The method further includes monitoring a data line, while maintaining at least a clock line in a low power mode, to detect at least one media access request generated by at least one component connected to the data line and to the clock line; and forcing the at least clock line to exit the low power mode and starting a contention prevention period, when the media access controller or at least one component requests to access the data line. Also disclosed is a device for implementing the method of media access control.

Device and method for media access control

A technique of operating a processor subsystem masks interrupts to the processor subsystem during a power-down sequence of a processor of the processor subsystem. A boot vector for the processor of the processor subsystem is set. The boot vector provides an address associated with a saved processor state. A current state of the processor is saved to provide the saved processor state. The technique determines whether one or more first masked interrupts occurred during the saving of the current state of the processor. The processor that is to be powered-down is stopped when the one or more first masked interrupts did not occur during the saving of the current state of the processor. The technique also determines whether one or more second masked interrupts occurred following the saving of the current state of the processor. The processor is powered-down when the one or more second masked interrupts did not occur following the saving of the current state of the processor.

Techniques for operating a processor subsystem to service masked interrupts during a power-down sequence

A method and apparatus for entering a low power mode is provided. In one embodiment, data processing system () has power control circuitry () which may be used to control power usage in data processing system (). Power mode select circuitry () may be used to select a power mode. Depending upon the power mode selected, power control circuitry () may use a cascaded approach to selecting which portions of data processing system () will be powered down, and thus how deeply data processing system () will be powered down.

Method and apparatus for entering a low power mode

An integrated circuit () includes a multiple voltage digital multiplexer circuit () for multiplexing digital signals provided at different supply voltage levels. In one form, the multiplexer () includes an analog multiplexer () for receiving the digital signals, a level shifter () coupled to the output of the analog multiplexer (), and a supply voltage multiplexer () for providing one of various supply voltages used on the IC corresponding to the signals being multiplexed. A control circuit () is used to control the input selection of the analog multiplexer () as well as the supply voltage multiplexer () for providing the correct supply voltage to the level shifter (). This provides the ability to multiplex digital signals of differing voltage levels onto a single pad on the IC ().

Multiplexing of digital signals at multiple supply voltages in an integrated circuit

A system and method of varying frequency is disclosed. A first oscillator in a phase-locked loop (PLL) maintains a first frequency as part of the PLL lock. A second oscillator having a control coupled to the PLL can be modified to generate a frequency different than that of the PLL. This is accomplished while maintaining lock of the PLL.

Frequency generating device and method thereof

A well bias controller receives input from a sensor. The sensor indicates when a desired threshold condition, such as a temperature or current limit has been exceeded. Threshold conditions are chosen so that when the threshold condition is exceeded, the amount of current drawn by the well bias circuit and through the transistor exceeds the amount of leakage current that would otherwise occur in the device if a well bias circuit were not used. Whenever it is determined, based on the threshold condition, that the well bias circuit is using more current than a device would otherwise leak, the controller turns the well bias circuit off.

System and circuit for controlling well biasing and method thereof

A low power differential signaling technique for reducing power in CMOS circuits. An input signal is provided to the input of a transmitter which uses transitions of the input signal to switch between two complementary resistive paths between upper and lower voltages across a common resistive element to develop a differential signal pair. In particular, during a high transition, a first pair of resistive switches are coupled across the common resistor causing current flow in a first direction and, during a low transition of the input signal, a second pair of resistive switches are coupled across the same common resistive element to cause current to flow in the opposite direction. The switching action converts a single-ended input signal to a differential signal pair across the common resistive element. The voltage swing across the differential signal pair is reduced to less than one half of the voltage differential between the upper and lower voltages which represent the source voltages. A receiver converts the differential signal pair back to a single-ended output voltage signal. The conversion of the single-ended input signal to a differential signal pair with a reduced voltage swing provides substantial power savings without the necessity of a voltage reference and further achieves the benefit of increased immunity to common mode noise.

Method and apparatus for low power differential signaling to reduce power

A differential charge and dump optoelectronic receiver for baseband digital optoelectronic data links is disclosed having a preamplifier and a voltage controlled current source that defines the tail current of a differential pair functioning as a two quadrant multiplier, and using capacitors as loads on the differential pair making said differential pair an integrator. The integrator provides a full differential output, part of which is fedback to control the gain of the preamplifier. In a preferred embodiment, one integrator pair is used to recover the data from a Manchester encoded data stream. In another preferred embodiment, two pairs of integrators are used for QPSK like codes.

Differential charge and dump optoelectronic receiver

A projection system for a computer has an electronic slide (94) that is coupled to an electronic image signal (84) from a processor (82) in the computer (50). Projection optics (102) focus an optical image from the electronic slide (94) onto a screen (58).

Projection system for a computer

One surface of a semiconductor component attached to one surface of a header with an opposite surface of the component having an optical input/output positioned adjacent one end of an optical fiber. The component and optical fiber are fixedly attached with no strain by a curable gel with the header acting as a heat sink. Electrical contacts are made to the component by means of leads formed on the header and/or a conductive coating deposited on the optical fiber.

Semiconductor to optical link

In accordance with a first aspect, a binding assay comprises a machine-readable storage medium which supports a molecular receptor (22). In accordance with a second aspect, a support member (50) supports first (22) and second (24) molecular receptors and first (26) and second (28) data identifying the molecular receptors (22,24). In accordance with a third aspect, a support member has a first annular portion (106) to support molecular receptors and a second annular portion (108) to support machine-readable data identifying the plurality of molecular receptors.

Binding assay methods

An optical hinge (20) provides one or more free space optical communication links through the hinge (17) of an instrument (10). The optical links include a transmitter (24) in one section (14) of the instrument (10) and a receiver (34) in the other section (16) of the instrument (10). An optical coupler (27) connects the transmitter (24) to the receiver (34) through a hinge (17).

Optical hinge

A process combines a high performance silicon pin diode (60) and other semiconductor devices such as transistors, resistors, and capacitors. The pin diode (60) is formed beneath an epitaxial layer (44) of the device at a depth that maximizes absorption of light having a wavelength greater than approximately 600 nanometers. Devices such as transistors are formed in the epitaxial layer (44). An integrated circuit has a substrate (41), an intrinsically doped layer (42), a buried layer (43), and an epitaxial layer (44). An isolation region (45) isolates an intrinsically doped region (46), a buried layer region (47), and the epitaxial layer region (48). The pin diode (32) has a substrate (41), an intrinsically doped region (46), and a buried layer region (47). A polysilicon region (62) provides a top side contact for the pin diode (60).

Optically sensitive device and method

A flexible electro-optic circuit board (20) includes a polymer circuit board (22) and a polymer optical backplane (34). The polymer circuit board (22) includes a plurality of circuit elements (50, 52). The polymer optical backplane (34) has a plurality of optical transmission lines (44). A plurality of optical vias (30) couple the polymer circuit board (22) to the polymer optical backplane (34).

Electro-optic device board

Growing community of inventors

Mesa, AZ, United States of America

Christopher K Chun