Micron Technology Incorporated

Intel Corporation

Lodestar Licensing Group LLC

Christopher Joseph Bueb

Poorna Kale

Sean Stephen Eilert

Olivier Duval

Ting Luo

Ashok Sahoo

Aravind Ramamoorthy

Kishore Kumar Muchherla

Harish Reddy Singidi

Jianmin Huang

Luca Porzio

Kulachet Tanpairoj

Preston Allen Thomson

Scott Anthony Stoller

John Edward Maroney

Tao Liu

Minjian Wu

Todd Legler

Tyson M Stichka

Cheng Cheng Ang

Gianluca Coppola

Eric Yuen

Ryan Laity

Wanmo Wong

Te-Chang Lin

Vincenzo Reina

Qi Dong

Manjunath Chandrashekaraiah

Shaul Halabi

Taufique Murad Ahmed

Sven Lehsten

A multi-interface memory can include a memory package that includes a memory device and host interfaces coupled to the memory device. Each of the host interfaces is configured to operate according to a different protocol. The memory package can be coupled to a host via one or more of the host interfaces. More than one of the host interfaces can share a contact.

Multi-interface memory

Methods, systems, and devices for techniques for data refresh based on environmental conditions are described. A memory system may program data to a set of blocks, where an order in which the data be programmed to respective blocks of the set of blocks may be based on a first block ordering. The memory system may also program respective indications of respective temperatures of the programming for the respective blocks. The memory system may identify, during a start-up procedure, a flag indicating to perform a refresh operation for the set of blocks. As such, the memory system may perform during the start-up procedure, the refresh operation for the set of blocks using a second block ordering. In some examples, the second block ordering may be based on the respective indications of the respective temperatures for the set of blocks.

Techniques for data refresh based on environmental conditions

Methods, systems, and devices for triggering a refresh for non-volatile memory are described. A host system may communicate with a memory system, where the host system and memory system may be included within a vehicle (e.g., an automotive system). The host system may receive an indication that the vehicle is powering down and may enter a power off state in response to the indication. The host system may detect a trigger (e.g., using a time or temperature input) to switch back to a power on state while the vehicle is powered down, the trigger associated with performing a refresh operation at the memory system. The host system may enter the power on state and may transmit a power on command to the memory system. The memory system may perform the refresh operation on one or more memory cells while the vehicle remains in the powered down state.

Triggering a refresh for non-volatile memory

Methods, systems, and devices for command prioritization techniques for reducing latency in a memory system are described. In some examples, a host system may receive a set of commands from one or more virtual machines to access a common memory system. The host system may store the set of command in a command queue associated with the memory system and arrange the set of command according to order that is based on one or more identified pattern of accessing sequential addresses in the set of commands. The host system may transmit the set of command to the memory system based on the order and the memory system may execute the commands according to the order.

Command prioritization techniques for reducing latency in a memory system

Methods, systems, and devices for techniques for priority information are described. A memory system may be configured to receive, at a memory system, an indication that data is critical to operating the memory system; receive the data that is critical to operating the memory system based at least in part on the indication; select one more parameters to provide a reliability of a storage of the data into a memory device of the memory system based at least in part on receiving the indication and receiving the data; and program the data into the memory device of the memory system using the one or more parameters based at least in part on selecting the one or more parameters.

Techniques for priority information

Methods, systems, and devices for techniques for temperature-based access operations are described. A memory system may be configured to write temperature information to metadata during a write operation. The temperature information may indicate a temperature range within which the memory system may be during the write operation. The memory system may perform a corresponding read operation based on the temperature information written to the metadata and a temperature of the memory system during the read operation. A server may determine and indicate parameters associated with writing the temperature information to the metadata. Additionally, or alternatively, the server may indicate trim parameters for use in performing read operations based on temperature information received from the memory system. In some examples, the memory system may perform targeted refresh operations at locations based on temperature information stored associated with the locations.

Techniques for temperature-based access operations

After data to be written to a storage device, such as a solid state drive (SSD), is received from a host system, the received data is encoded using a first error correction code to generate first parity data. A temperature at which memory cells of the storage device will store the received data is determined. In response, a first portion of the received data is identified (e.g., data in memory storage that is error-prone at a predicted higher temperature that has been determined based on output from an artificial neural network using sensor(s) input). The first portion is encoded using a second error correction code to generate second parity data. The second error correction code has a higher error correction capability than the first error correction code. The encoded first portion, the first parity data, and the second parity data are stored in the memory cells.

Data reliability for extreme temperature usage conditions in data storage

Methods, systems, and devices supporting an interface for refreshing non-volatile memory are described. In some examples, a host system may communicate with a memory system, where both the host system and the memory system may be included within a vehicle (e.g., an automotive system). The host system may receive an indication that the vehicle is powering down (e.g., shutting off an engine or lowering power output from a battery). The host system may switch from a first mode corresponding to a first power usage to a second mode corresponding to a second, lower power usage in response to the vehicle powering down, the second mode supporting initiation of a refresh operation at the memory device. The host system may transmit a refresh command to the memory system to refresh non-volatile memory while the vehicle is powered down if the host system is operating in the second mode of operation.

Interface for refreshing non-volatile memory

A vehicle-based apparatus for noise injection and monitoring includes a first processing device coupled to a plurality of components and a second processing device coupled to the plurality of components. The second processing device injects noise into at least one component among the plurality of components and monitors behavior of the at least one component in response to the injected noise. The second processing device determines, based, at least in part, on the monitored behavior of the at least one component responsive to the injected noise, a susceptibility to the injected noise exhibited by the at least one component and transmits signaling indicative of the determined susceptibility to the injected noise exhibited by the at least one component to the first processing device.

Vehicle-based apparatus for noise injection and monitoring

A host system can be queried to determine whether new data has been received based on a first time interval. After completion of the first time interval, a determination can be made as to whether the new data has been received and whether a portion of the new data was not stored. In response to the portion of the new data not being stored, the host system can be queried to determine whether subsequent data has been received based on a second time interval where the second time interval is different from first time interval.

Adjustable garbage collection suspension interval

Methods, systems, and devices for techniques to refresh memory systems operating in low power states are described. The memory system may operate in a first power mode that includes deactivation of a voltage rail that supplies power to the memory system. The memory system may receive the power over the voltage rail during a time period that the memory system is operating in the first power mode. In some cases, the memory system may determine that the power may be received for a duration and a command is not received during that duration. The memory system may perform a self-refresh operation based on determining that the duration indicated by the timer expires without receiving a command.

Techniques to refresh memory systems operating in low power states based on temperature

A technique to control write operations in a logical partition. For example, a device can receive a user specified write threshold for the logical partition that is hosted on a pool of memory cells shared by a plurality of logical partitions in wear leveling. An accumulated amount of data written into the memory cells according to write requests addressing the logical partition is tracked. In response to the accumulated amount reaches the write threshold, further write requests addressing the logical partition can be blocked, rejected, and/or ignored. For example, the logical partition can be used to buffer data for time shift in playing back content streaming from a server. Write operations for time shift can be limited via the user specified threshold to prevent overuse of the total program erasure budget of the pool of memory cells shared with other logical partitions.

Write budget control of time-shift buffer for streaming devices

A solid state drive having a drive aggregator and a plurality of component solid state drive, including a first component solid state drive and a second component solid state drive. The drive aggregator has at least one host interface, and a plurality of drive interfaces connected to the plurality of component solid state drives. The drive aggregator is configured to generate, in the second solid state drive, a copy of a dataset that is stored in the first component solid state drive. In response to a failure of the first component solid state drive, the drive aggregator is configured to substitute a function of the first component solid state drive with respect to the dataset with a corresponding function of the second component solid state drive, based on the copy of the dataset generated in the second component solid state drive.

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Folsom, CA, United States of America

Christopher Joseph Bueb