International Business Machines Corporation

Christopher Jon Johnson

Philip Heidelberger

Cyriel Johan Minkenberg

Tolga Ozguner

Lonny Lambrecht

Kerry Christopher Imming

Bogdan Prisacari

Wolfgang Emil Denzel

German Rodriguez Herrera

Baba L Arimilli

Jean Louis Calvignac

Marco C Heddes

Joseph Franklin Logan

A multiprocessor computer system includes a plurality of processor nodes and at least a three-tier hierarchical network interconnecting the processor nodes. The hierarchical network includes a plurality of routers interconnected such that each router is connected to a subset of the plurality of processor nodes; the plurality of routers are arranged in a hierarchy of n&#x2267;3 tiers (T, . . . , T); the plurality of routers are partitioned into disjoint groups at the first tier T, the groups at tier Tbeing partitioned into disjoint groups (of complete Tgroups) at the next tier Tand a top tier Tincluding a single group containing all of the plurality of routers; and for all tiers 1&#x2266;i&#x2266;n, each tier-Tsubgroup within a tier Tgroup is connected by at least one link to all other tier-Tsubgroups within the same tier Tgroup.

Interconnection network topology for large scale high performance computing (HPC) systems

Embodiments of the present invention provide systems, methods and articles of manufacture for displaying semiconductor components in a graphical user interface and manipulating the position of semiconductor components. Embodiments of the present invention may check the placement of components against a plurality of placement rules and determine if a component is legally placed or aligned on the semiconductor structure in the x direction, the y direction, or both the x and y directions. Embodiments of the present invention may display the properly placed and misplaced components in a graphical user interface. Furthermore, embodiments of the present invention may display the components in different colors, each color corresponding to the placement rule or rules which the current component placement violates. Furthermore, embodiments of the present invention may provide tools to aid in the repositioning of a component or components, in an effort to satisfy violated design rules.

Method and apparatus to visually assist legalized placement with non-uniform placement rules

A method and apparatus are provided for implementing multiple configurable sub-busses of a point-to-point bus. Each of a plurality of bus interconnects include a transmit interface and a receive interface connected to the point-to-point bus. Each transmit interface includes a transmit buffer and a serializer coupled between the buffer and the point-to-point bus. The transmit buffer provides an asynchronous interface between a transmit source and the serializer. The serializer receives data and control signals from the transmit buffer at a first frequency and transmits data and control signals over the point-to-point bus at a higher second frequency. Transmit steering logic is coupled between the transmit source and each transmit buffer of the plurality of bus interconnects. Transmit steering logic directs data and control signals from transmit source to each selected one of the transmit buffers based upon a selected bus configuration.

Method and apparatus for implementing multiple configurable sub-busses of a point-to-point bus

A method and apparatus are provided for implementing chip-to-chip interconnect bus initialization. The chip-to-chip interconnect bus includes first and second unidirectional buses for full duplex communications between two chips. A lower than normal bus frequency is used during the initialization process. A transmit initialization sequencer of a source transmits predefined SYNC symbols on the connected unidirectional bus. A receive initialization sequencer of a destination chip checks for a defined number of valid SYNC or IDLE symbols. When the receive initialization sequencer of a destination detects the defined number of valid SYNC or IDLE symbols, the receive initialization sequencer triggers a transmit initialization sequencer of the destination to transmit IDLE symbols on the connected unidirectional bus. The transmitted IDLE symbols are detected by a receive initialization sequencer at the source, indicating that both ends of the interconnect bus have synchronized. Once link synchronization is established, the source transmits configuration information to the destination using normal bus messages. Programmable delay elements and configuration registers are set.

Method and apparatus for implementing chip-to-chip interconnect bus initialization

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Rochester, MN, United States of America

Christopher Jon Johnson