Sandisk Technologies Inc.

Sandisk 3d LLC

Gtat Corporation

Matrix Semiconductor, Inc.

Sunrise Memory Corporation

Twin Creeks Technologies, Inc.

Cypress Semiconductor Corporation

Sandisk Corporation

Western Digital Technologies, Inc.

Christopher John Petti

Roy E Scheuerlein

S Brad Herner

Tanmay Kumar

Andrew J Walker

Abhijit Bandyopadhyay

Scott Brad Herner

Mohamed M Hilali

Yangyin Chen

Perumal Ratnam

Luca Giovanni Fasoli

Calvin K Li

Eli Harari

Yoichiro Tanaka

Gerrit Jan Hemink

Yung-Tin Chen

Venkatesan Murali

Tianhong Yan

Steven J Radigan

Siu Lung Chan

Federico Nardi

Sayeef Salahuddin

Juan Pablo Saenz

Robert D Norman

George Samachisa

Luiz M Franca-Neto

Thomas H Lee

Mark G Johnson

Theodore H Smick

Khandker N Quader

Wu-Yi Henry Chien

Mac D Apodaca

Gopalakrishna B Prabhu

Usha Raghuram

Samuel Vance Dunton

Zhiyong Li

Raghuveer S Makala

Johann Alsmeier

Deepanshu Dutta

James K Kai

James Montague Cleeves

Peter Rabkin

Rahul Sharangpani

Jiahui Yuan

Fei Zhou

Henry Chien

Yu-Chung Lien

Vivek Subramanian

Adarsh Rajashekhar

Michael Grobis

Alper Ilkbahar

Xinde Hu

Daniel Bedau

Xiying Costa

Akio Nishida

Gopal Prabhu

James E Nulty

Paul Michael Farmwald

Andre N Stolmeijer

Sucheta Nallamothu

Eran Sharon

Yingda Dong

Idan Alrod

Masaaki Higashitani

Steven M Zuniga

Ariel Navon

Dana Lee

Mark Alan Helm

Man Lung Mui

Jayavel Pachamuthu

Neil Leslie Robertson

Tong Zhang

Ward M Parkinson

Yao-Sheng Lee

Martin Aureliano Hassner

Jordan Asher Katine

Wei Zhao

Mark Harold Clark

N Johan Knall

Igor G Kouznetsov

Masanori Tsutsumi

Chun-Ming Wang

Steven Patrick Maxwell

Tz-Yi Liu

Ali K Al-Shamma

Nathan Franklin

Shinsuke Yada

Michael A Vyvoda

Cathal G Phelan

Yoocharn Jeon

Chi-Ming Wang

Derek Stewart

Ashish Pancholy

Daxin Mao

Zhenyu Lu

Zhida Lan

Yuji Takahashi

Takuya Futase

Srikanth Ranganathan

Kun Hou

An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings.

Device with embedded high-bandwidth, high-capacity memory using wafer bonding

A thin-film storage transistor in a NOR memory string has a gate dielectric layer that includes a silicon oxide nitride (SiON) tunnel dielectric layer. In one embodiment, the SiON tunnel dielectric layer has a thickness between 0.5 to 5.0 nm thick and an index of refraction between 1.5 and 1.9. The SiON tunnel dielectric layer may be deposited at between 720° C. and 900° C. and between 100 and 800 mTorr vapor pressure, using an LPCVD technique under DCS, NO, and NHgas flows. The SiON tunnel dielectric layer may have a nitrogen content of 1-30 atomic percent (at %).

Silicon oxide nitride tunnel dielectric for a storage transistor in a 3-dimensional NOR memory string array

A semiconductor memory device is implemented as strings of storage transistors, where the storage transistors in each string have drain terminals connected to a bit line and gate terminals connected to respective word lines. In some embodiments, the semiconductor memory device includes a reference bit line structure to provide a reference bit line signal for read operation. The reference bit line structure configures word line connections to provide a reference bit line to be used with a storage transistor being selected for read access. The reference bit line structure provides a reference bit line having the same electrical characteristics as an active bit line and is configured so that no storage transistors are selected when a word line is activated to access a selected storage transistor associated with the active bit line.

Quasi-volatile memory with reference bit line structure

A method is provided that includes reading a plurality of resistance-switching memory cells comprising a block of data, decoding the block of data using an error correction code decoder, and based on results of the decoding, selectively performing an overwrite-read process to read the block of data. The overwrite read process determines a change in resistance of the resistance-switching memory cells in response to a write pulse.

Overwrite read methods for resistance switching memory devices

Thin-film Ferroelectric field-effect transistor (FeFET) may be organized as 3-dimensional NOR memory string arrays. Each 3-dimensional NOR memory string array includes a row of active stack each including a predetermined number of active strips each provided one on top of another and each being spaced apart from another by an isolation layer. Each active strip may include a shared source layer and a shared drain layer shared by the FeFETs provided along the active strip. Data storage in the active strip is provided by ferroelectric elements that can individually electrically set into one of two polarization states. FeFETs on separate active strips may be configured for read, programming or erase operations in parallel.

Three-dimensional memory string array of thin-film ferroelectric transistors

A semiconductor memory device implements a write disturb reduction method to reduce write disturb on unselected memory cells by alternating the order of the write logical '1' step and write logical “0” step in the write operations of selected memory cells associated with the same group of bit lines. In one embodiment, a method in an array of memory cells includes performing write operation on the memory cells in one of the memory pages to store write data into the memory cells where the write operation includes a first write step of writing a data of a first logical state and a second write step of writing data of a second logical state; and performing the write operation for each row of memory cells by alternately performing the first write step followed by the second write step and performing the second write step followed by the first write step.

Semiconductor memory device with write disturb reduction

Memory device including modular memory units and modular circuit units for concurrent memory operations

3-dimensional memory string array of thin-film ferroelectric transistors

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive word line layers located over a substrate, and a plurality of vertical memory strings. Each vertical memory string includes a series connection of a memory stack structure and a selector element. Each of the memory stack structures extends through the alternating stack and includes a respective memory film and a respective vertical semiconductor channel. Each of the selector elements includes a two terminal device that is configured to provide at least two different resistivity states.

Three-dimensional NAND memory device containing two terminal selector and methods of using and making thereof

A memory element is provided that includes a portion of a bit line plug, a portion of a source line plug, a portion of a word line, a portion of a vertical semiconductor pillar disposed between the bit line plug, the source line plug and adjacent the word line, and a gate oxide including a ferroelectric material disposed between the vertical semiconductor pillar and the word line.

Three dimensional ferroelectric memory

A non-volatile memory uses phase change memory (PCM) cells in a three dimensional vertical cross-point structure, in which multiple layers of word lines run in a horizontal direction and bit lines run in a vertical direction. The memory cells are located in a recessed region of the word lines and are separated from the bit line by an ovonic threshold switch. A surfactant lining of the word line recess in which the phase change memory material is placed improves stability of the resistance state of the memory cells, allowing for improved multi-state operation.

Methods of forming a phase change memory with vertical cross-point structure

Magnetic random-access memory (MRAM) circuits are provided herein. In one example implementation, an MRAM circuit includes control circuitry coupled to a magnetic tunnel junction (MTJ) element in series with a selector element. This control circuitry is configured to adjust current through the selector element when the selector element is in a conductive state. The circuit also includes a compensation circuitry configured to compensate for a offset voltage across the selector element in the conductive state based on adjustments to the current through the selector element. An output circuit is also configured to report a magnetization state of the MTJ element.

Magnetic random-access memory with selector voltage compensation

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Mountain View, CA, United States of America

Christopher John Petti