Agere Systems Inc.

Lucent Technologies Inc.

Agere Systems Guardian Corp.

Other

Christopher John Nicol

Patrik Larsson

Mark Andrew Bickerstaff

Kanwar Jit Singh

Dominic Wing-Kin Yip

Bing Xu

Ravi Kumar Kolagotla

Ran-Hong Yan

Alexander Goldovsky

Oliver Ridler

Charles Nicholas Alexander Thomas

Tomasz Thomas Prokop

Matthew Besz

Tracy C Denk

A method of operating a communications circuit with at least one control channel and at least one data channel includes the steps of monitoring the at least one control channel, powering a receiver portion of the circuit when the at least one control channel indicates that data is to be received, and refraining from powering the receiver portion when the at least one control channel indicates that data is not to be received. The circuit can operate, for example, under the 3GPP HSDPA standard. Where desired, the clock and power supply to the receiver portion and a bit rate processing portion can be independently gated.

Communications circuit and method with reduced power consumption

A communications circuit can operate with a data channel and a control channel. A changeable portion of the circuit can be reconfigurable between a first mode associated with activity on the control channel only and a second mode associated with activity on both the data channel and the control channel. The first mode can be selected to reduce power consumption compared to the second mode. Controller circuitry is provided to sense signals associated with the control channel and to switch the changeable portion between the first and second modes.

Reconfigurable communications circuit operable with data channel and control channel

A communications circuit can operate in a first mode, such as a diversity mode including space time transmit diversity (STTD). In this mode, a number of equalizer filter portions connected to a number of post-equalizer processors are employed. When the diversity mode is not required, the extra equalizer filter portions would represent a waste of power consumption and/or chip space. A combining circuit and suitable control circuitry are provided to allow use of the additional equalizer filter portions to be made in other operating modes. Appropriate trade-offs can be made based on power consumption and performance.

Reconfigurable communications circuit

The present invention discloses a single unified decoder for performing both convolutional decoding and turbo decoding in the one architecture. The unified decoder can be partitioned dynamically to perform required decoding operations on varying numbers of data streams at different throughput rates. It also supports simultaneous decoding of voice (convolutional decoding) and data (turbo decoding) streams. This invention forms the basis of a decoder that can decode all of the standards for TDMA, IS-95, GSM, GPRS, EDGE, UMTS, and CDMA2000. Processors are stacked together and interconnected so that they can perform separately as separate decoders or in harmony as a single high speed decoder. The unified decoder architecture can support multiple data streams and multiple voice streams simultaneously. Furthermore, the decoder can be dynamically partitioned as required to decode voice streams for different standards.

Reconfigurable architecture for decoding telecommunications signals

A partial carry-save format is employed for a finite impulse response filter output representation, thereby reducing a number of flip-flops and hence power. By replacing the least significant bit processing section on the output side of the finite impulse response filter with a combined carry-save adder and carry-propagate adder followed by a register rather than two flip-flops, the present invention reduces the load on the clock and achieves reduced propagation delay. To further improve the performance of the finite impulse response filter, a simpler carry-save adder is employed in the least significant bit section, which is possible due to the use of a single register at an input to each of the carry-save adders rather than two flip-flops, one for a carry output and one for a sum output from the adder. The combination of a reduction of half of the flip-flops and a replacement of a simpler carry-save adder for each of the carry-save adders results in a significant improvement in the overall filter performance and power and space consumption.

High-speed/low power finite impulse response filter

A system and method for echo and near end cross talk (E/N) cancellation in a communications system using a pair of FIR filter ICs, wherein a first FIR filter IC filters a plurality of low amplitude E/N signals and a first portion of a plurality of data bits of a plurality of high amplitude E/N signals, and a second FIR filter IC filters a second portion of the data bits of the high amplitude E/N signals which cannot be filtered by the first FIR filter IC. The output values from the two filters are then summed to produce the E/N cancellation signal. The present invention allows for the use of lower bit-resolution, lower power consumption, and less expensive filter ICs than conventional FIR filters implemented in a single IC.

System and method for filtering echo/NEXT signal interferrence

The present invention discloses a butterfly processor capable of performing convolutional decoding and LogMAP decoding in telecommunications systems. First and second add-compare-select modules are provided for receiving input path metrics. A branch metric calculator is also provided for receiving input data and extrinsic data. The branch metric calculator generates output branch metrics to each of the first and second add-compare-select modules. Each of the add-compare-select modules includes a log-sum correction means coupled to compare and select components. A controllable switch selectively couples outputs of the select components and the log-sum corrections means to enable either one of convolutional or LogMAP decoding.

Butterfly processor for telecommunications

Multiported register files used for storing coefficients in adaptive FIR are improved upon by implementing a split memory architecture that has the ability to separately control the least significant bits and the most significant bits of coefficient values that are stored in the filter. When the filter is operated to use so-called &ldquo;burst mode&rdquo; updating, the updating circuitry of the filter can be disabled and only the most significant bits of the coefficients are read out from the multiported register file while the least significant bits remain unchanged. This conserves power without sacrificing precision, since only certain ones of the bits of the coefficients are used in the multiplication of the sample. In addition, when only the most significant bits of the coefficients are being cycled through the register filter, any changing bits are prevented from being supplied to the updating circuit, so that the updating circuit performs no computation at all, rather than performing one that is discarded. Advantageously, using such improved multiported register files, adaptive FIR filters can be constructed which operate with lower power consumption.

Multiported register file for burst mode coefficient updating

A partial carry-save format is employed for a finite impulse response filter output representation, thereby reducing a number of flip-flops and hence power. By replacing the least significant bit processing section on the output side of the finite impulse response filter with a combined carry-save adder and carry-propagate adder followed by a register rather than two flip-flops, the load on the clock can be reduced, thereby achieving reduced propagation delay. To further improve the performance of the finite impulse response filter, a simpler carry-save adder is employed in the least significant bit section, which is possible due to the use of a single register at an input to each of the carry-save adders rather than two flip-flops, one for a carry output and one for a sum output from the adder. The combination of a reduction of half of the flip-flops and a replacement of a simpler carry-save adder for each of the carry-save adders results in a significant improvement in the overall filter performance and power and space consumption.

Multiported register files for use in storing coefficients in adaptive FIR filters. incorporate computational ability, e.g., the ability to perform computation on coefficient values or derivatives thereof, or to control the operations performed thereon. For example, a multiported register file may incorporate an overflow/underflow detection and/or saturation unit. Also, the multiported register file may incorporate a special encoder to speed up the multiplication process, e.g., the so-called &ldquo;Booth&rdquo; encoder. Likewise, the multiported register file may incorporate a converter for changing the representation of the coefficients, e.g., a two's complement to sign-magnitude converter. All computation performed in the multiported register file is performed outside of the critical path of the filtering or of the coefficient updating. Using such improved multiported register files, adaptive FIR filters can be constructed which operate faster, and with lower power consumption.

Multiported register file for coefficient use in filters

An n-bit prefix tree adder includes n prefix trees, each associated with a bit position of the adder and including a number of computation stages. In accordance with an illustrative embodiment of the invention, the prefix trees are interconnected such that carry signals are computed at least partially in parallel. For example, a carry signal computed in an initial stage of a given prefix tree is used in subsequent stages of the given prefix tree without introducing substantial additional delay in computation of other carry signals in other prefix trees associated with higher bit positions. Carries computed for lower bit positions are thus used to compute carries for higher bit positions, but generate, propagate and/or transmit signals may be generated in an initial stage of each of the prefix trees without utilizing a primary carry input signal in the computation. The resulting adder architecture provides reduced logic depth, delay and circuit area relative to conventional architectures.

Prefix tree adder with efficient carry generation

A cache implements bank-by-bank locking to keep critical code from being flushed out of the cache. A register is maintained to rank the banks from the most recently used to the least recently used. Ordinarily, when code needs to be moved into the cache, the least recently used bank is flushed, the code is moved into that bank, and the register is updated to identify that bank as the most recently used. However, if a bank is designated in a bypass vector as being locked, that bank is bypassed in the maintenance of the register and is thus never identified as the bank to be flushed.

Method and memory cache for cache locking on bank-by-bank basis

Multiported register files are employed to implement the input delays necessary for finite impulse response (FIR) filter operation. A multiported register file is a memory, typically small, with at least one read port and one write port. Data written into the multiported register file may be read out therefrom in any desired order. The multiported register tile may have additional output ports from which the data stored therein may be read out, also in any desired order, and independent from the order of any other output port. At least one output of each multiported register file is coupled to the input of the next stage of the FIR filter, if any. In addition, each multiported register file feeds data from one output to the multiply-add portion of its associated stage of the FIR filter. When the introduction of at least one sample delay for a particular sample is necessary, the multiported register file storing that sample is operated to supply, as an output, data that was previously stored therein, regardless of any data currently being supplied to it as input. In contrast, when no sample delay is required for a particular sample to reach a particular multiported register file, the multiported register files in the path of that sample are operated in a lookthrough mode. The read and write addresses, as well as the write enable signals for each multiported register file may be supplied in a pipelined manner.

Filter structure and method

The NEG output of the Booth encoding circuit and the multiplicand input are gated so as to minimize switching activity in the multiplier without adding any delay to the critical path thereof. Advantageously, power consumption in the multiplier is significantly reduced, e.g., on the order of 90%, when multiplication is in fact not being performed. Additionally, by changing the structure of the last XOR gate of the partial product generation circuit, the need to gate the multiplicand input can be eliminated. Advantageously, this eliminates the extra circuitry which would otherwise be required to gate the multiplicand input, thus reducing cost. Furthermore, additional power savings may be achieved by efficiently resynchronizing the multiplicand input with the Booth encoded input to the partial product circuit.

Low power multiplier for CPU and DSP

Improved operation of multi-processor chips is achieved by dynamically controlling processing load of chips and controlling, significantly greater than on/off granularity, the operating voltages of those chips so as to minimize overall power consumption. A controller in a multi-processor chip allocates tasks to the individual processors to equalize processing load among the chips, then the controller lowers the clock frequency on the chip to as low a level as possible while assuring proper operation, and finally reduces the supply voltage. Further improvement is possible by controlling the supply voltage of individual processing elements within the multi-processor chip, as well as controlling the supply voltage of other elements in the system within which the multi-processor chip operates.

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Red Bank, NJ, United States of America

Christopher John Nicol