Micron Technology Incorporated

Other

Christopher John Kawamura

Scott James Derner

Charles L Ingalls

Tae Hyoung Kim

Howard Kirsch

Mitsunari Sukekawa

Sanh D Tang

Daniele Vimercati

Umberto Di Vincenzo

Huy Thanh Vo

Eric S Carman

Jiyun Li

Brenton P Van Leeuwen

Hiroaki Taketani

Yusuke Yamamoto

Yuan He

Martin Brox

Christopher K Morzano

Beau D Barry

J Wayne Thompson

C Omar Benitez

Luoqi Li

Johnathan L Gossi

Methods of operating memory devices are disclosed. A method may include activating a first, target word line. The method may also include coupling a second word line adjacent the first, target word line to an associated first main word line while the first, target word line is activated. Further, the method may include coupling the associated main word line to a negative word line voltage while the first, target word line is activated. Associated circuits, devices, and systems are also disclosed.

Memory device control schemes, and associated methods, devices, and systems

Memory devices are disclosed. A device may include a number of word line drivers, wherein each word line driver of the number of word line drivers including a first transistor and a second transistor. The device may also include a number of first driver gates, wherein the first transistor of each word line driver has a gate coupled to a dedicated first driver gate of the number of driver gates. Further, the device may include a second driver gate coupled to a gate of each second transistor of each of the number of word line drivers. Associated circuits, methods, and systems are also disclosed.

Word line driver circuitry including shared driver gates, and associated methods, devices, and systems

Methods, systems, and apparatuses for storing operational information related to operation of a non-volatile array are described. For example, the operational information may be stored in a in a subarray of a memory array for use in analyzing errors in the operation of memory array. In some examples, an array driver may be located between a command decoder and a memory array. The array driver may receive a signal pattern used to execute an access instruction for accessing non-volatile memory cells of a memory array and may access the first set of non-volatile memory cells according to the signal pattern. The array driver may also store the access instruction (e.g., the binary representation of the access instruction) at a non-volatile subarray of the memory array.

Storing memory array operational information in non-volatile subarrays

An apparatus may include a sense amplifier with a single column select transistor, a local input/output line selectively couplable to a first bit line through the column select transistor, and a read/write gap comprising at least a first transistor and a second transistor. The first transistor may be couplable to a read select signal and a complimentary local input/output line and the second transistor is couplable to the complimentary local input/output line and a global input/output line.

Single column select architecture for sense amplifier circuity

Apparatuses, systems, and methods for compensated sense amplifier with cross-coupled n-type transistors. A sense amplifier has a pair of p-type transistors coupled between a system voltage and respective first and second gut nodes. When a command signal is active, the p-type transistors are coupled in a diode fashion from the system voltage to the respective gut nodes. The amplifier also has a pair of n-type transistors which are cross coupled, where a first n-type transistor has a node coupled to the first gut node and a gate coupled to the second gut node and the second n-type transistor has a node coupled to the second gut node and a gate coupled to the first gut node. Each of the n-type transistors may have a separate current flowing through them and respective one of a pair of feedback transistors to a ground voltage.

Apparatuses and methods for compensated sense amplifier with cross coupled N-type transistors

Apparatuses, systems, and methods for single-ended sense amplifiers. A memory device may include a number of sense amplifiers used to read the voltage of memory cells along digit lines. Double-ended sense amplifiers are coupled to two digit lines. Single-ended sense amplifiers are coupled to a single digit line. The memory cells of an edge word line of a memory array may alternately be coupled to a single-ended sense amplifier or a double-ended sense amplifier. The use of single-ended sense amplifiers may reduce a footprint for a given number of memory cells in the array.

Apparatuses and methods for single-ended sense amplifiers

A memory device includes multiple memory cells configured to store data. The memory device also includes multiple digit lines each configured to carry data to and from a respective memory cell. The memory device further includes multiple sense amplifiers each selectively coupled to respective digit lines and including first and second NMOS transistors and first and second gut nodes coupled to the first and second NMOS transistors, respectively. Each sense amplifier is configured to perform threshold compensation for the first and second NMOS transistors by storing respective voltages at the first and second gut nodes that are proportional to the respective threshold voltages of the first and second NMOS transistors. The sense amplifier also amplifies a differential voltage between the first and second gut nodes by charging the first gut node and discharging the second gut node based at least in part on respective charges of the digit lines.

Pre-sense gut node amplification in sense amplifier

Methods, systems, and devices for techniques for generating access line voltages are described. A system may use a first voltage supply and a second voltage supply that is configured to supply a lower voltage than the first voltage supply. The system may activate a first circuit to couple a node with the first voltage supply so that a first voltage develops on the node from the first voltage supply. The system may activate a second circuit to couple the node with the second voltage supply so that a second voltage that is lower than the first voltage develops on the node from the second voltage supply.

Generating access line voltages

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. In some examples, multi-level accessing, sensing, and other operations for ferroelectric memory may be based on sensing multiple charges, including a first charge associated with a dielectric of the memory cell and a second charge associated with a polarization of the memory cell. In some cases, multi-level accessing, sensing, and other operations may be based on transferring a first charge associated with a dielectric of the memory cell to a sense amplifier, isolating the sense amplifier, activating the sense amplifier, transferring a second charge associated with a polarization of the memory cell to the sense amplifier, and activating the sense amplifier a second time.

Multi-level storage in ferroelectric memory

Some embodiments include a memory device having a buried wordline, a shield plate, and an access device. The access device includes first and second diffusion regions and a channel region. The diffusion regions and the channel region are arranged vertically so that the channel region is between the first and second diffusion regions. The wordline is adjacent to a first side surface of the channel region, and the shield plate is adjacent to a second side surface of the channel region; with the first and second side surfaces being in opposing relation to one another. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies comprising memory cells and shielding material between the memory cells

Apparatuses and methods are disclosed that include ferroelectric memory and for operating ferroelectric memory. An example apparatus includes a capacitor having a first plate, a second plate, and a ferroelectric dielectric material. The apparatus further includes a first digit line and a first selection component configured to couple the first plate to the first digit line, and also includes a second digit line and a second selection component configured to couple the second plate to the second digit line.

Apparatuses and methods including ferroelectric memory and for operating ferroelectric memory

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory device may maintain a digit line voltage at a ground reference for a duration associated with biasing a ferroelectric capacitor of a memory cell. For example, a digit line that is in electronic communication with a ferroelectric capacitor may be virtually grounded while a voltage is applied to a plate of the ferroelectric capacitor, and the ferroelectric capacitor may be isolated from the virtual ground after a threshold associated with applying the voltage to the plate is reached. A switching component (e.g., a transistor) that is in electronic communication with the digit line and virtual ground may be activated to virtually ground the digit line and deactivated to isolate the digit line from virtual ground.

Ferroelectric memory cell sensing

An access line multiplexor can be formed under vertically stacked tiers of memory cells. The multiplexor can include a first transistor coupled to a vertical access line, to a horizontal access line, and to a second transistor. The second transistor can be coupled to a power supply. The transistors can be n-type metal oxide semiconductor transistors.

Vertical access line multiplexor

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be initialized to a first state and a second ferroelectric memory cell may be initialized to a different state. Each state may have a corresponding digit line voltage. The digit lines of the first and second ferroelectric memory cells may be connected so that charge-sharing occurs between the two digit lines. The voltage resulting from the charge-sharing between the two digit lines may be used by other components as a reference voltage.

Growing community of inventors

Boise, ID, United States of America

Christopher John Kawamura