Intel Corporation

Christopher John Haid

Rodney R Rozman

Jerry A Kreifels

Vishram P Dalvi

Jahanshir J Javanifard

Jeffrey J Peterson

Jeff Evertt

Joseph W Tsang

Peter K Hazen

Charles W Brown

Alan E Baker

David A Leak

Thomas C Price

Edward M Babb

Fasil G Bekele

Mase J Taub

Sanjay S Talreja

Robert E Larsen

Enrico David Carrieri

Bharat M Pathak

Marcus E Landgraf

Tahmid U Rahman

Vishram Prakash Dalvi

A flash memory device including a first memory array, a control circuit coupled to the first memory array, and a second independent memory array coupled to the control circuit. The first memory array includes a plurality of memory blocks each having a memory cell. The memory cell may be a nonvolatile flash memory cell. The control circuit controls the programming, erasing, and reading of the memory cells. The second memory array includes a plurality of block lock-bits each corresponding to one of the plurality of memory blocks. The state of each block lock-bit indicates whether the memory cell in the corresponding memory block is locked. The second memory array may also include a master lock-bit that indicates whether the block lock-bits are locked.

Block locking apparatus for flash memory

A non-volatile memory array such as a flash memory array may include a power savings circuit to control a stand-by mode of the non-volatile memory array. The power savings circuit may cause a placement of the non-volatile memory array into a stand-by mode in the absence of activity on at least one or more inputs of the non-volatile memory array. Power may be saved automatically without processor intervention by reducing the operating current of the non-volatile memory array. The automatic power savings circuit may provide a chip enable output to an input of stand-by circuitry to control the operation of the standby circuitry without requiring an explicit stand-by command from a processor.

Automatic power savings stand-by control for non-volatile memory

A method and apparatus to read information from a content addressable memory (CAM) cell of a nonvolatile memory is provided. The apparatus may be a nonvolatile memory that may include a first content addressable memory (CAM) cell, wherein the first CAM cell comprises a latch to store volatile binary information and to provide the volatile binary information to an output terminal of the first CAM cell.

Method and apparatus to read information from a content addressable memory (CAM) cell

A method and apparatus suspend a program operation in a nonvolatile writeable memory. The nonvolatile writeable memory includes a memory array, a command register and memory array control circuitry. The command register decodes a program suspend command and provides a suspend signal as an output. The memory array control circuitry is coupled to receive the suspend signal from the command register. The memory array control circuitry performs a program operation in which data is written to the memory array. The memory array control circuitry suspends the program operation upon receiving the suspend signal.

Nonvolatile writeable memory with program suspend command

A flash memory device including a first memory array, block locking circuitry, and control circuitry. The memory array includes a plurality of memory blocks each having a memory cell. The block locking circuitry includes a plurality of block lock-bits and a master lock-bit. Each block lock-bit corresponds to one of the plurality of memory blocks and indicates whether the corresponding memory block is locked. The master lock-bit indicates whether the plurality of block lock-bits are locked. The control circuitry is configured to receive a passcode that causes the control circuitry to override the master lock-bit. The control circuitry may also be configured to receive a passcode that causes the control circuitry to override one of the block lock-bits.

Block locking and passcode scheme for flash memory

A method and apparatus for reseting, for example, a Flash electrically erasable programmable read-only memory (EEPROM) having a microcontroller, the method and apparatus receiving a reset signal and, in response to said reset signal: determining if said microcontroller is performing an algorithm that manipulates a voltage and if said microcontroller is performing such an algorithm, performing a first operation to change the voltage, and performing a second operation to reset a logic.

Apparatus for performing a user requested reset during algorithm

A method of writing to flash memory cells in a flash memory device. The flash memory device includes a first memory array and a second independent memory array. The first memory array includes memory blocks each having a memory cell. The second independent memory array includes block lock-bits each corresponding to one of the memory blocks. The method of writing to a memory cell in one of the memory blocks of the first memory array includes the steps of issuing a command to write to the memory cell, determining if a corresponding block lock-bit in the second independent memory array is set, and writing to the memory cell if the corresponding block lock-bit is not set.

Method of programming, erasing, and reading block lock-bits and a master

A method and apparatus suspend a program operation in a nonvolatile writeable memory. The nonvolatile writeable memory includes a memory array, a command register, and memory array control circuitry. The command register decodes a program suspend command and provides a suspend signal as an output. The memory array control circuitry is coupled to receive the suspend signal from the command register. The memory array control circuitry performs a program operation in which data is written to the memory array. The memory array control circuitry suspends the program operation upon receiving the suspend signal.

Method and apparatus for suspending the writing of a nonvolatile

A power supply lockout circuit that prevents corruption of nonvolatile writeable memory data is described. The power supply lockout circuit monitors the power supply signals from several power supplies. The power supply lockout circuit locks out commands writing to the nonvolatile writeable memory when any one of the monitored power supply signals coupled to the nonvolatile writeable memory is below a specified signal level. The power supply lockout circuit includes a detector which provides a lockout signal to the nonvolatile writeable memory when a power supply signal is less than a prespecified voltage. The power supply lockout circuit also includes a sampling circuit which provides other lockout signals to the nonvolatile writeable memory when a different power supply signal is less than a reference voltage.

Growing community of inventors

Folsom, CA, United States of America

Christopher John Haid