Ltx Corporation

Ltx-credence Corporation

Xcerra Corporation

Christopher Joel Hannaford

Phillip D Burlison

Mark E Deome

Tommie Edward Berry

David W Curry

Eric H Rosenfeld

David Menis

Kenneth J Lanier

Roger W Blethen

H Neil Kelly

Jeffrey H Perkins

Edward J Terrenzi

Michael Carlyle Davis

Solomon Max

R Warren Necoechea

Donald Vick Organ

Roger Henry Therrien

Michael Gordon Davis

Lisette J Zarzalejo

Richard McCarthy

A high voltage connector assembly includes a plurality of pin assemblies, each of the plurality of pin assemblies having a first end and a second end. The first end of each of the plurality of pin assemblies is configured to releasably electrically engage a load board. A plurality of pin pads, wherein the second end of each of the plurality of pin assemblies is configured to electrically engage a pin pad included within the plurality of pin pads. A plurality of connector pads are electrically coupled to the plurality of pin pads, wherein each of the plurality of connector pads is configured to be electrically coupled to a wire-based conductor included within a plurality of wire-based conductors. A potting compound is configured to encapsulate the plurality of connector pads.

Connector / cable assembly

A method for identifying and reducing spurious frequency components is provided. A method in accordance with at least one embodiment of the present disclosure may include generating a digital sinusoidal waveform at a direct digital synthesizer (DDS) and receiving the digital sinusoidal waveform at an audio digital-to-analog converter. The method may further include converting the digital sinusoidal waveform to an analog sinusoidal waveform containing spurious frequency components, combining the analog sinusoidal waveform with an analog distortion correction waveform to generate a composite output waveform and receiving the composite output waveform at notch filter circuitry. The method may also include filtering the composite output waveform to generate a filtered composite output waveform and amplifying a difference between the filtered composite output waveform and a signal from a circuit-under-test (CUT) to generate an amplified analog signal. The method may also include converting the amplified analog signal to an amplified digital signal. Of course, additional implementations are also within the scope of the present disclosure.

Method and apparatus for identifying and reducing spurious frequency components

A system, method, and apparatus for distortion analysis is provided. A method in accordance with at least one embodiment of the present disclosure may include receiving a clock frequency at a direct digital synthesizer (DDS) and generating at least one stream of phase numbers via said DDS. The method may further include generating a digital sine wave using, at least in part, said clock frequency and said at least one stream of phase numbers. Of course, additional implementations are also within the scope of the present disclosure.

System, method, and apparatus for distortion analysis

An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.

Single platform electronic tester

An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patters to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.

Growing community of inventors

Norwood, MA, United States of America

Christopher Joel Hannaford