Honeywell International Inc.

Christopher Jay Matthews

Ross Merritt

Michael Ray Elgersma

Scott I Snyder

Todd Loren Braman

Timothy Merrill Buck

Christopher A Lund

Pedro Luis Lebron

James B Oven

Tom Jakel

Richard S Russell

Steven Edward Peter

Dang Tu Van-Cao

A sensor assembly is disclosed. The sensor assembly includes a housing that includes a top housing and a bottom housing that clamp together. The sensor assembly also includes a printed circuit board assembly (PBA). The sensor assembly also includes at least one piece of elastic material that is located in between the top housing and the PBA and in between the bottom housing and the PBA. When the PBA is clamped in the housing, the sensor assembly allows the PBA to maintain alignment relative to the housing across different environments in order to enable proper operation of the sensor assembly. A top surface of the PBA and a bottom surface of the PBA each have at least one three-dimensional feature that is designed to increase friction with the elastic material.

Isolating sensor assembly using elastic material

An Inertial Navigation System (INS) testing system includes a Unit Under Test (UUT) with an INS module, a DAT tool configured to provide command and control functions to a user, and a Dynamically Integrated Navigation Tester (DINT) in communication with the UUT and the DAT tool. The DINT includes a truth data conversion module configured to receive truth data and convert it to navigation data suitable for transmission to the UUT. The INS testing system advantageously allow a user to interface with a UUT while providing user-specified dynamic inputs from the DINT with the truth data selected by the user.

Dynamically integrated navigation tester

A multiple processor architecture with flexible external input/output interface is provided. In one embodiment, an open flexible processor architecture avionics device comprises: a multiple processor architecture having a primary processor, a secondary processor, a random access memory (RAM) coupled to at least the secondary processor, and a shared memory coupled to the primary and secondary processor; and a flexible input/output (I/O) interface coupled to the multiple processor architecture, wherein the flexible I/O interface provides I/O access to the primary processor using a fixed I/O protocol, and provides I/O access to the secondary processor using at least one re-configurable I/O protocol; wherein the primary processor is dedicated to executing embedded software for implementing a primary base functionality, the primary processor has read and write access to the shared memory, and the primary processor is not reprogrammable; and wherein the secondary processor has read-only access to the shared memory and is programmable.

Multiple processor architecture with flexible external input/output interface

A system comprises a plurality of reference navigation systems, each reference navigation system configured to generate a respective reference navigation solution. The system also comprises a test navigation system, the test navigation system configured to generate a test navigation solution; and a processing unit configured to compare the test navigation solution to each of the respective reference navigation solutions to estimate one or more errors in the differences between the test navigation solution and the respective reference navigation solutions. The processing unit is further configured to update the respective reference navigation solutions to account for the corresponding one or more estimated errors. The processing unit is also configured to compare the test navigation solution to the updated reference navigation solutions to generate a performance score representative of the performance of the test navigation system.

Multiple truth reference system and method

Growing community of inventors

Minneapolis, MN, United States of America

Christopher Jay Matthews