Extreme Networks, Inc.

Apple Inc.

Christopher J Young

Erik R Swenson

David K Parker

Michael Yip

Keith Alan Cox

Manu Gulati

Parin Patel

Cyril De La Cropte De Chanterac

Nitin Bhandari

Derek Fujio Iwamoto

Charles Frederick Burton, Iii

Michael M Yip

A method and apparatus for providing telemetry for use in power control functions is disclosed. A system includes an integrated circuit (IC) having a first power management circuit. The IC also includes a number of functional circuit blocks within a number of different power domains. A second power management circuit is implemented external to the IC and includes a number of voltage regulators. Each of the power domains is coupled to receive power from one voltage regulators. During operation, the first power management circuit may send commands requesting the change of one or more voltages provided to the IC. The second power management circuit may respond by performing the requested voltage change(s), and may also provide telemetry data to the first power management circuit. The second power management circuit may also provide telemetry data responsive to receiving a no operation command from the first power management circuit.

Method and apparatus for providing telemetry for power management functions

A programmable processor configured to perform one or more packet modifications through execution of one or more commands. A pipelined processor core comprises a first stage configured to selectively shift and mask data in each of a plurality of categories in response to one or more decoded commands, and combine the selectively shifted and masked data in each of the categories. The pipelined processor core further comprises a second stage configured to selectively perform one or more operations on the combined data from the first stage and other data responsive to the one or more decoded commands. In one implementation, the processor is implemented as an application specific integrated circuit (ASIC).

Packet data modification processor

Packet modification is performed in the switch fabric by selecting a conditional command belonging to a set of commands for modifying a packet. The set of commands is identified based on an index value, and selecting a conditional command belonging to the set of commands is based on a mask value, where the index and mask values are determined based on data in the packet undergoing modification, such as the packet's source and destination, or incoming label. Among other advantages, controlling packet modification in the switch fabric through selecting a conditional command belonging to a set of commands allows multiple sets of commands to be replaced with a single set of commands, resulting in a more efficient use of available external memory.

Command selection in a packet forwarding device

A processor readable medium storing a data structure for supporting one or more packet modification operations is provided. The data structure has a pointer to a sequence of one or more commands stored in a first memory area and implementing one or more packet modification operations. The data structure also has a pointer to a burst of one or more data or mask items stored in a second memory area for use by the one or more commands. A method of performing one or more packet modification operations on a packet is also provided. This packet is associated with a data structure link. In this method, a data structure corresponding to the data structure link is retrieved. This data structure has the format described above. A packet modification system utilizing a data structure having this format is also provided.

Data structures for supporting packet data modification operations

A packet processing system architecture and method are provided. According to a first aspect of the invention, a plurality of quality of service indicators are provided for a packet, each with an assigned priority, and a configurable priority resolution scheme is utilized to select one of the quality of service indicators for assigning to the packet. According to a second aspect of the invention, wide data paths are utilized in selected areas of the system, while avoiding universal utilization of the wide data paths in the system. According to a third aspect of the invention, one or more stacks are utilized to facilitate packet processing. According to a fourth aspect of the invention, a packet size determiner is allocated to a packet from a pool of packet size determiners, and is returned to the pool upon or after determining the size of the packet. According to a fifth aspect of the invention, a packet is buffered upon or after ingress thereof to the system, and a packet for egress from the system assembled from new or modified packet data and unmodified packet data as retrieved directly from the buffer. According to a sixth aspect of the invention, a system for preventing re-ordering of packets in a packet processing system is provided. A seventh aspect of the invention involves any combination of one or more of the foregoing.

Packet processing system architecture and method

Disclosed is a system and method for assembling a data packet. The system can be implemented as four memory elements associated with one or more processors. The first memory element stores a sequence number and a sub-channel identifier for an incoming data packet. The second memory element stores a revised packet fragment. The third memory element stores an unrevised packet fragment. The fourth memory element stores a starting address. In the system, the starting address may be the starting address of the revised packet fragment or the unrevised packet fragment wherein the first memory element identifies portions of the fourth memory element associated with the sequence number. The one or more processors are configured to create a modified data packet by combining the unrevised packet fragments and the revised packet fragment, wherein the modified data packet is associated with the sequence number and sub-channel identifier.

System and method for assembling a data packet

A packet processing system architecture and method are provided. According to a first aspect of the invention, packet parser functions are distributed throughout a packet processing system comprising a packet classification system and a packet modification system. According to a second aspect of the invention, an egress mirroring function is provided to the system. According to a third aspect of the invention, a multi-dimensional quality of service indicator for a packet is provided. According to a fourth aspect of the invention, a cascaded combination of multiple, replicated packet processing systems is used to process a packet. A fifth aspect of the invention involves any combination of one or more of the foregoing.

Disclosed herein are a system and method for status monitoring, including debug error detection, during data packet processing. In general terms, the system for status monitoring during data packet processing can be implemented as a system including a packet processor and a buffer. The packet processor generates processing data based on one or more control structures while revising packet data. The packet processor generates the processing data while performing one or more lookup cycles. The buffer records the processing data and the status of the one or more control structures. The processing data includes a lookup number and the lookup number identifies the number of cycles performed by the packet processor.

System and method for packet processor status monitoring

A command instruction set for a packet data modification processor has a format in which a packet address, if present, specifies an encapsulated layer within the packet and a location within this encapsulated layer. The at least one command within the command instruction set specifies deriving at least a portion of a first packet from data taken from a second packet or the command.

Packet data modification processor command instruction set

Systems of and methods for processing data for communication between a sender and a receiver are described. In one embodiment, the phase of a first clock is used to select between first and second portions of data from the sender. The selected data is then synchronized, for communication to the receiver, to a second clock having a frequency which is an integer multiple of that of the first clock, wherein the integer multiple is two or more. The first and second portions of the data may be provided to the same output pins in this embodiment for communication to the receiver. In a second embodiment, first and second portions of data from the sender are clocked in using first and second edges, respectively, of a first clock. The first and second edges have a first polarity if a first pre-determined mode is in effect, and have a second polarity if a second pre-determined mode is in effect. Data derived from the clocked in data is then synchronized, for communication to the receiver, to a second clock. In a third embodiment, data from the sender is clocked in using a first clock. The clocked in data is then transformed responsive to a pre-determined mode selected from a plurality of possible modes. The transformed data is then synchronized, for communication to the receiver, to a second clock. In a fourth embodiment, a first clock is provided which is delayed relative to a second clock by a pre-determined amount. Data is then clocked out for communication to a receiver using the second clock, and clocked in for communication back to the sender using a third clock derived from the second clock. Data derived from the clocked in data is then synchronized to the first clock.

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San Jose, CA, United States of America

Christopher J Young