Intel Corporation

Christopher J Shannon

Ganapati Srinivasa

Mark Rowland

Glenn J Hinton

Per H Hammarlund

Ronak Singhal

Hermann Gartler

In one embodiment, the present invention includes a method for receiving a cache access request for data present in a lower-level cache line of a lower-level cache, and sending recency information regarding the lower-level cache line to a higher-level cache. The higher-level cache may be inclusive with the lower-level cache and may update age data associated with the cache line, thus reducing the likelihood of eviction of the cache line. Other embodiments are described and claimed.

Synchronizing recency information in an inclusive cache hierarchy

A cache line replacement protocol for selecting a cache line for replacement based at least in part on the inter-cache traffic generated as a result of the cache line being replaced.

Method, system, and apparatus for an hierarchical cache line replacement

A technique for intelligently evicting cache lines within an inclusive cache architecture. More particularly, embodiments of the invention relate to a technique to evict cache lines within an inclusive cache hierarchy based on the cache coherency traffic generated between an upper level cache and lower level caches.

Growing community of inventors

Hillsboro, OR, United States of America

Christopher J Shannon