Compaq Computer Corporation, Inc.

Hewlett-packard Development Company, L.p.

Christopher J Pettey

Dwight D Riley

Brian S Hausauer

Thomas R Seeman

Bassam N Elkhoury

John M MacLaren

Paul R Culley

Alan L Goodrum

Peter J Michels

S Paul Olarig

A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ('AGP') bus and host and memory buses, as a bridge between an additional registered peripheral component interconnect ('RegPCI') bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional RegPCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional registered PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request (&#x201c;REQ&#x201d;) and Grant (&#x201c;GNT&#x201d;) signal lines for each PCI device utilized on the additional registered PCI bus. Selection of the type of bus bridge (AGP or RegPCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test (&#x201c;POST&#x201d;). Software configuration may also be determined upon detection of either an AGP or a RegPCI device connected to the common AGP/RegPCI bus.

Device adapted to send information in accordance with a communication protocol

Device operating according to a communication protocol

High speed peripheral interconnect apparatus, method and system

A high speed connection apparatus, method, and system is provided for peripheral components on digital computer systems. The peripheral component interconnect (PCI) specification is used as a baseline for an extended set of commands and attributes. The extended command and the attribute are issued on the bus during the clock cycle immediately after the clock cycle when the initial command was issued. The extended commands and attributes utilize the standard pin connections of conventional PCI devices and buses making the present invention backward-compatible with existing (conventional) PCI devices and legacy computer systems. The conventional PCI command encoding is modified and the extended command is used to qualify the type of transaction and the attributes being used by the initiator of the transaction. The extended commands are divided into four groups based upon the transaction type and the extended command type. Transactions are either byte count or byte-enable transaction types. Extended command types are either validated or immediate. Some extended command encodings are reserved but can be assigned in the future to new extended commands that will behave predictable with current devices.

Computer system with registered peripheral component interconnect device for processing extended commands and attributes according to a registered peripheral component interconnect protocol

A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-EISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. The system bus is superpipelined, in that transactions overlap. A fast burst transactions are allowed between the bridge and main memory, i.e., requests which can be satisfied without deferring or retrying are applied to the system bus without waiting to get a response from the target. A range of addresses (e.g., system memory addresses) is defined to be a fast burst range, and any address in this range is treated differently compared to addresses outside the range. The bridge is programmed, by configuration cycles, to establish this fast burst range, within which it is known that an out-of-order response will not be received. When a transaction reaches the bridge interface from the bridge or PCI bus, and it is recognized that the address is within the range, then the fast burst mode is allowed, and write addresses are allowed to follow one another without the delay for the snoop phase or the possibility of defer or retry.

Bus-to-bus bridge in computer system, with fast burst memory range

A computer system including synchronous dynamic random access memory (SDRAM) circuits that are capable of operating at different frequencies. A memory controller generates multiple clock signals with appropriate frequencies for use by the SDRAM memory devices. Asynchronous data queues are used to provide data transfers between the SDRAM memory and the processor or other bus master devices residing on a peripheral bus. Upon initialization, the computer system determines the type of SDRAM devices present and provides status information to the memory controller which, in response, generates appropriate clock signals to the SDRAM memory circuits.

Memory controller supporting DRAM circuits with different operating

A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E)ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. According to a feature of the invention, provision is made for split transactions, i.e., a read request which is not satisfied while the processor requesting it is still on the bus, but instead the bus is relinquished and other transactions intervene before the read result is available. A contemporary microprocessor such as a P6 has a deferred transaction protocol to implement split transactions, but this protocol is not available on a PCI bus. Split transactions are done by a 'retry' command on a PCI bus, wherein a read request that cannot be completed immediately is queued and a 'retry' response is sent back to the requester on the bus; this instructs the requester to retry (send the same command again) at a later time. To avoid a situation where two processors issue locked cycles which are enqueued and retried in separate bridges, a 'Superlock' signal is added to the processor bus, which is asserted by a bridge as soon as a locked transaction is enqueued, and thereafter neither bridge will accept a locked cycle issued by a processor, other than that locked read that was initiated by a processor and enqueued in the bridge and is being retried.

Lock protocol for PCI bus using an additional 'superlock' signal on the

A system and method of transferring data on a data bus is disclosed. The system includes a data bus agent having a storage medium connectable to a data bus and arranged to store data and a bus agent device adapted to receive data from the storage medium. The method includes driving a signal on a data bus by a first bus agent, sampling the signal at a second bus agent, storing the sampled signal in a storage medium associated with the second bus agent, and processing the stored signal at the second bus agent.

Data bus agent including a storage medium between a data bus and the bus

A computer system includes a data storage device on the first data bus, a device on the second data bus, and a bridge device capable of storing multiple data transactions for delivery from the second data bus to the first data bus. The bridge device includes a first data storage buffer preassigned to one of the transactions held in the bridge, and a buffer management element that assigns, if necessary, a second data storage buffer to the data transaction when the data associated with the transaction overflows the first data storage buffer.

Bridge circuit comprising independent transaction buffers with control

The computer system includes a data storage device on a first data bus, a requesting device on a second data bus that initiates a request to read data from a cache line in the data storage device, beginning at a location not aligned with a first boundary of the cache line and including all remaining data in the cache line up to a second boundary. The computer system also includes a bridge device that retrieves the entire cache line from the data storage device but provides only the requested data to the requesting device.

Aligning a memory read request with a cache line boundary when the

A computer system includes a memory device on the first data bus, a device that initiates on a second data bus a write transaction that can involve less than an entire cache line of data, and a bridge device that automatically converts the write transaction into one that requires an entire cache line of data and delivers the converted transaction to the first data bus.

Receiving a write request that allows less than one cache line of data

A computer system includes a data storage device on a first data bus, a requesting device that initiates a delayed request on a second data bus, and a bridge device that delivers the delayed request to the first data bus and, after the requesting device regains control of the second data bus, begins providing data to the requesting device while the data storage device is providing the requested data to the bridge device.

Providing data from a bridge to a requesting device while the bridge is

A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E) ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. According to a feature of the invention, provision is made for split transactions, i.e., a read request which is not satisfied while the processor requesting it is still on the bus, but instead the bus is relinquished and other transactions intervene before the read result is available. A contemporary microprocessor such as a P6 has a deferred transaction protocol to implement split transactions, but this protocol is not available on a PCI bus. Split transactions are done by a 'retry' command on a PCI bus, wherein a read request that cannot be completed immediately is queued and a 'retry' response is sent back to the requester on the bus; this instructs the requester to retry (send the same command again) at a later time.

Growing community of inventors

Houston, TX, United States of America

Christopher J Pettey