International Business Machines Corporation

Adeia Semiconductor Bonding Technologies Inc.

Globalfoundries Inc.

Adeia Semiconductor Solutions LLC

Tessera LLC

Christopher J Penny

Lawrence Alfred Clevenger

Michael Rizzolo

Benjamin David Briggs

Nicholas Anthony Lanzillo

Huai Huang

Robert Russell Robison

Brent A Anderson

Kisik Choi

Sean David Burns

Marc Adam Bergendahl

Sivananda K Kanakasabapathy

Roger Allan Quon

Nicole A Saulnier

Christopher Joseph Waskiewicz

James J Demarest

Bartlet H Deprospo

Elbert Emin Huang

Hosadurga K Shobha

Takeshi Nogami

Matthew Earl Colburn

Nelson M Felix

Yann A M Mignot

Deepika Priyadarshini

Koichi Motoyama

Leigh Anne H Clevenger

Aldis G Sipolins

Junli Wang

Son Van Nguyen

Theodorus E Standaert

Griselda Bonilla

Joe Lee

Jonathan R Fry

Jean E Wynne

Kangguo Cheng

Chih-Chao Yang

Veeraraghavan S Basker

Stephen McConnell Gates

Somnath Ghosh

Zhenxing Bi

Krishna R Tunga

Mahmoud Amin

Dimitri R Kioussis

David V Horak

Steven J Holmes

Shom Ponoth

Charles W Koburger, Iii

Oscar Van Der Straten

Wai-Kin Li

Yunpeng Yin

Shyng-Tsong Chen

James John Kelly

Raghuveer Reddy Patlolla

Samuel S Choi

Anuja E DeSilva

Benjamin D Briggs

Leigh Anne Hodges Clevenger

Loma Vaishnav

Chanro Park

Balasubramanian Pranatharthiharan

Ekmini Anuja De Silva

Hsueh-Chung Chen

Xunyuan Zhang

Yann Mignot

Terry Allen Spooner

Ashim Dutta

Cornelius Brown Peethala

Timothy Mathew Philip

Yang Liu

Youngseok Kim

Matthew S Angyal

Shariq Siddiqui

Habib Hichri

Patrick D Watson

Craig Child

Brown Cornelius Peethala

Keith Donegan

Abraham Arceo De La Pena

Rohit Galatage

Martin O'Toole

Brendan O'Brien

David K Watts

Sean D Burns

Stefania Axo

Mark Christopher Wallen

Elbert Huang

Han You

Bryan Gury

Matthew E Colburn

Roger A Quon

Jae O Choo

Adam L Da Silva

A semiconductor structure and method of manufacturing a semiconductor structure having a front side and an opposing backside. An early power delivery network (EBPDN) of wires is built above a substrate layer. Buried power rails (BPRs) are built above levels of the PDN and connected to the EBPDN by short length via connections that can be self-aligned to the back side buried power rails. Both BPRs and vias connections have a common metallization. A front side level of transistor devices are built at the front side of the structure above the BPRs. The resulting formed buried power rail structure has an aspect ratio of height:width greater than 4:1, a height >3 times a height of the formed via structure; and a via structure having a length greater than a height of the formed conductive power rail structure.

Early backside first power delivery network

An etch back air gap (EBAG) process is provided. The EBAG process includes forming an initial structure that includes a dielectric layer disposed on a substrate and a liner disposed to line a trench defined in the dielectric layer. The process further includes impregnating a metallic interconnect material with dopant materials, filling a remainder of the trench with the impregnated metallic interconnect materials to form an intermediate structure and drive-out annealing of the intermediate structure. The drive-out annealing of the intermediate structure serves to drive the dopant materials out of the impregnated metallic interconnect materials and thereby forms a chemical- and plasma-attack immune material.

Self-forming barrier for use in air gap formation

A method of forming a mandrel for use in a pitch doubling process is provided in which a metal hard mask is inserted between a mandrel material layer and a soft mask. The insertion of the metal hard mask allows for easier pattern transfer into the mandrel material layer and avoids many issues encountered during multi-patterning steps. The insertion of the metal hard mask forms a square mandrel that has a flat top due to durability against etch and ability to wet strip the metal hard mask. The metal hard mask can be tuned before pattern transfer into the underlying mandrel material layer to provide a hard mask pattern that is smaller or larger than the pattern without performing such tuning. The method also can be used to protect the downstream non-mandrel processes where selectivity is crucial.

Metal hard mask for precise tuning of mandrels

Integrated chips include first lines, formed on an underlying substrate. Spacers are formed conformally on sidewalls of the plurality of lines. Etch stop remnants are positioned on the sidewalls of the plurality of lines, between the spacers and the underlying substrate. Second lines are formed on the underlying substrate, between respective pairs of adjacent first lines.

Single-mask alternating line deposition

A method is presented forming a fully-aligned via (FAV) and airgaps within a semiconductor device. The method includes forming a plurality of copper (Cu) trenches within an insulating layer, forming a plurality of ILD regions over exposed portions of the insulating layer, selectively removing a first section of the ILD regions in an airgap region, and maintaining a second section of the ILD regions in a non-airgap region. The method further includes forming airgaps in the airgap region and forming a via in the non-airgap region contacting a Cu trench of the plurality of Cu trenches.

Selective ILD deposition for fully aligned via with airgap

An apparatus comprising a dielectric layer located between a first electrode and a second electrode and a third electrode located on the dielectric layer between the first electrode and the electrode, wherein the first electrode is separated from a first side of the third electrode by a first portion of the dielectric layer, and the second electrode is separated from a second side of the third electrode by a second portion of the dielectric layer.

Horizontal RRAM device and architecture for variability reduction

A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.

Self aligned pattern formation post spacer etchback in tight pitch configurations

A technique relates to an integrated circuit (IC). The IC includes a conductive line formed on a conductive via, the conductive line being formed though a dielectric material. The IC includes an etch stop layer having one or more extended portions intervening between one or more edge portions of the conductive line and the conductive via, the one or more edge portions being at a periphery of the conductive line and the conductive via, the etch stop layer including a higher dielectric breakdown than the dielectric material. The one or more extended portions of the etch stop layer cause the conductive line to be formed with a bottom part having a reduced dimension than an upper part of the conductive line.

Top via interconnect having a line with a reduced bottom dimension

An interconnect structure for an integrated circuit includes a plurality of first-type interconnect elements and a second-type of interconnect element which directly contact an underlying first-type interconnect element. The second-type interconnect element extends along a first axis to define a horizontal length and along a second axis to define a vertical height. The second-type interconnect element and the first-type interconnect element define a conductive via comprising a metal material extending continuously along the second axis from a base of the underlying first-type interconnect element and stopping at the upper surface of the second-type interconnect element. The vertical height of the second-type interconnect element is greater than the vertical height of the first-type interconnect elements.

Interconnects having spacers for improved top via critical dimension and overlay tolerance

A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.

Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device

A method of forming a top via is provided. The method includes forming a sacrificial trench layer and conductive trench plug in an interlayer dielectric (ILD) layer on a conductive line. The method further includes forming a cover layer on the ILD layer, sacrificial trench layer, and conductive trench plug, and forming a sacrificial channel layer and a conductive channel plug on the conductive trench plug. The method further includes removing the cover layer and the ILD layer to expose the sacrificial trench layer and the sacrificial channel layer. The method further includes removing the sacrificial trench layer and the sacrificial channel layer, and forming a barrier layer on the conductive channel plug and conductive trench plug.

Top via with damascene line and via

Embodiments of the invention provide a method that includes forming an IC layer having an inactive region and an active region. The active region includes a device-under-fabrication (DUF). The inactive region includes a geometric feature having a geometric shape. A film is deposited over the active DUF and the geometric feature such that a first portion of the film will be part of the active DUF, and such that a second portion of the film is over the geometric feature. A geometric shape of the film over the geometric feature matches the geometric shape of the geometric feature. Determining a thickness of the film is based at least in part a difference between a footprint of the geometric shape of the film and a footprint of the geometric shape of the geometric feature.

Conformal film thickness determination using angled geometric features and vertices tracking

An approach providing a semiconductor wiring structure with a self-aligned top via on a first metal line and under a second metal line. The semiconductor wiring structure includes a plurality of first metal lines in a bottom portion of a first dielectric material. The semiconductor wiring structure includes a top via in a top portion of the first dielectric material, where the top via is over a first metal line of the plurality of first metal lines. The semiconductor wiring structure includes a second dielectric material above each of the plurality of first metal lines except the first metal line of the plurality of first metal lines. Furthermore, the semiconductor wiring structure includes a second metal line above the top via, wherein the second metal line is in a third dielectric material and a hardmask layer that is under the third dielectric material.

Top via process with damascene metal

A method of forming fully aligned top vias is provided. The method includes forming a fill layer on a conductive line, wherein the fill layer is adjacent to one or more vias. The method further includes forming a spacer layer selectively on the exposed surface of the fill layer, wherein the top surface of the one or more vias is exposed after forming the spacer layer. The method further includes depositing an etch-stop layer on the exposed surfaces of the spacer layer and the one or more vias, and forming a cover layer on the etch-stop layer.

Fully aligned top vias

Embodiments of the present invention are directed to fabrication methods and resulting interconnect structures having a conductive thin metal layer on a top via that promotes the selective growth of the next level interconnect lines (the line above). In a non-limiting embodiment of the invention, a first conductive line is formed in a dielectric layer. A via is formed on the first conductive line and a seed layer is formed on the via and the dielectric layer. A surface of the seed layer is exposed and a second conductive line is deposited onto the exposed surface of the seed layer. In a non-limiting embodiment of the invention, the second conductive line is selectively grown from the seed layer.

Top via with next level line selective growth

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Saratoga Springs, NY, United States of America

Christopher J Penny