Finisar Corporation

Rambus Inc.

Christopher J Madden

Lewis B Aronson

Mark J Farley

Dan Case

Rudy Hofmeister

Tom Lenosky

Kim Burchiel

Shaun F Morrison

Richard E Perego

Jade M Kizer

An automatically ejecting magazine device includes an ammunition magazine which is substantially hollow for receiving ammunition for a firearm. A follower is movably disposed within the ammunition magazine to support ammunition for the firearm and a magnet is attached to the follower. A door is hingedly attached to the ammunition magazine and the door has a recess which is engaged by a magazine release of the firearm to retain the ammunition magazine in the firearm. The magnet urges the door into a disengaged position such that the recess is not accessible to the magazine release. In this way the ammunition magazine can drop out of the firearm when the last round of ammunition is fed into the firearm.

Automatically ejecting magazine device

A transceiver module having integrated eye diagram opening functionality for reducing jitter is described. The transceiver module may include a transmitter eye opener and a receiver eye opener integrated in a single circuit. The transceiver module may also include serial control and various other integrated components. Other functionalities that may be integrated on the transceiver module include loopback modes, bypass features, bit error rate testing, and power down modes.

Transceiver module and integrated circuit with dual eye openers

A system, among other embodiments, includes a memory controller having an integrated BER circuit and a plurality of memory devices. The memory controller also includes a control circuit and an interface having at least one transmit circuit to provide write data to at least one of the memory devices and at least one receive circuit to receive read data from at least one of the memory devices. The BER circuit includes a request generator circuit that outputs a request for a memory transaction. A request multiplexer selectively outputs a memory request to the interface from the request generator circuit or the control circuit. A data generator circuit outputs corresponding write data. A first write multiplexer selectively outputs the write data to the interface from the data generator circuit or the control circuit. A read multiplexer selectively receives read data from the receive circuit. The data generator circuit also outputs corresponding write data to a comparator circuit via a second write multiplexer. The comparator circuit outputs an error signal in response to a comparison of the received read data and corresponding stored write data. A counter outputs a count value indicating the number of errors (or bit errors) in response to the error signal. A register interface accesses the count value in the counter and a register that output one or more select signals during a mode of operation. The register interface also allows for controlling the data generator and request generator circuits.

Memory controller and method for operating a memory controller having an integrated bit error rate circuit

A transceiver module having integrated eye diagram opening functionality for reducing jitter is described. The transceiver module may include a transmitter eye opener and a receiver eye opener integrated in single circuit. The transceiver module may also include serial control and various other integrated components. Other functionalities that may be integrated on the transceiver module include loopback modules, bypass features, bit error rate testing, and power down modes.

Transceiver module and integrated circuit with dual eye openers and integrated loopback and bit error rate testing

A transceiver module having intergrated eye diagram opening functionality for reducing jitter is describe. The transceiver module may transmitter eye opener and a receiver eye opener integrated in a single circuit. The transceiver module may also include serial control and various other integrated components. Other functionalities that may be integrated on the transceiver module include loopback modes, bypass features, bit error rate testing, and power down mode.

Transceiver module and integrated circuit with multi-rate eye openers and bypass

An apparatus and method provides prediction of BER for an interface between ICs, such as a processor and a memory device, without using special test equipment. A known data pattern or PRBS is transmitted to a receiver, which compares the received data values with expected data values to determine if a bit error has occurred in an embodiment of the present invention. A center of data eye and the edge of the data eye are sampled (over sampled) in order to determine if a bit error has occurred in an alternate embodiment of the present invention. A first counter is used to count the total number of bits sampled and the second counter is used to count the number of errors that occurred in the total number of bits sampled.

Growing community of inventors

Los Altos, CA, United States of America

Christopher J Madden