Intel Corporation

Christopher J Lake

Michael N Derr

Shaun M Conrad

Reuven Rozic

William Knolla

Bhushan Vaidya

Yitschak Kapschitz

Efraim Rotem

Mikal Hunsaker

Nir Rosenzweig

Yoni Aizik

Zhenyu Zhu

Tomer Ziv

Esfir Natanzon

Michael C Wu

Arik Gihon

Pronay Dutta

Yevgeni Sabin

Nimrod Angel

Hem Doshi

Paul D Crutcher

Ido Melamed

Yoav Ben-Raphael

Chen Ranel

Patrick Douglas James

Kie Woon Lim

Natanel Abitan

Dhinesh Sasidaran

Prashant Kodali

Jared W Havican

Reena Patel

Vijay Degalahal

Justin Madigan

Vaibhav Shankar

Madhu Thangaraj

Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

Device, method and system for transparently changing a frequency of an interconnect fabric

Techniques and mechanisms for a power management circuit to monitor a power domain during one or more attempts to configure a low power state of the power domain. In an embodiment, the one or more attempts are performed during an instance of a local power state at a processor that is coupled to the power management circuit. The monitoring is to detect for a condition wherein the power domain has been in a power state, other than the low power state, for longer than a predetermined threshold length of time. Where the condition is detected, the power management circuit generates one or more signals which change the local power state of the processor, or interrupt an operating system that is executed with the processor. In another embodiment, the power management circuit provides analytic data based on the monitoring of the one or more attempts.

Power management circuitry for controlling a power state transition based on a predetermined time limit

Techniques and mechanisms for identifying a power state to be provided with an integrated circuit (IC). In an embodiment, evaluator circuitry of a system-on-chip is programmable based on multiple criteria which are each for a different respective power mode. Programming of the evaluator circuitry enables concurrent evaluations each to determine, for a different respective power mode, whether a detected state of the IC is able to accommodate said power mode. Results of the evaluations are communicated, in parallel with each other, to circuitry which selects one such power mode based on relative priorities of the power modes with respect to each other. In another embodiment, the evaluator circuitry comprises an array of circuit cells which are configurable each to perform a different respective evaluation based on a corresponding combination of a test condition and a detected condition of the IC.

Device, system and method to determine a power mode of a system-on-chip

One embodiment includes hardware logic to: receive first and second communications corresponding to an intellectual property (IP) core and begin a timed session in response to receiving the second communication; determine the firmware has completed processing the second communication before expiration of the timed session and increase a latency state corresponding to a resource in response to determining the firmware has completed processing the second communication before expiration of the timed session; receive a third communication corresponding to the IP core and begin an additional timed session in response to receiving the third communication; determine the firmware failed to complete processing the third communication before expiration of the additional timed session and decrease the latency state corresponding to the resource in response to determining the firmware failed to complete processing the third communication before expiration of the additional timed session.

System, apparatus and method for latency monitoring and response

A method implemented by a system on a chip (SOC) system executing an enhance serial peripheral interconnect (eSPI) master. The method to receive an alert from an eSPI slave, send a get out of band message to the eSPI slave, and receive an out of band message from the eSPI slave including a connection or disconnection command. The method enabling the SOC to include an embedded multiplexor for managing the role of a universal serial bus (USB) Type-C connector.

Inband messaging method for integrated type-C universal serial bus detection using enhanced serial peripheral interconnect

A power button override allows a persistent memory enabled platform to preserve data in persistent memory before initiating shutdown in a manner that is transparent to the user. The power button override prevents shutdown until all of the volatile cache and any other data in the platform has been flushed to persistent memory.

Power button override for persistent memory enabled platforms

Embodiments of computer-implemented methods, systems, computing devices, and computer-readable media are described herein for transitioning a computing device between a first state in which the computing device uses a first amount of power and a second state in which the computing device uses a second, greater amount of power. The computing device may include a shared wake pin to which a first external device and a second external device may be operably coupled, and a communication bus to which the first external device is connected and the second external device is not. Responsive to receipt of a wake signal at the wake pin, the computing device may transition between states, send an instruction to the first external device over the communication bus, and determine whether the first or second external device initiated the wake signal based on a response at the wake pin.

Determination of wake signal initiation on shared wake pins in computing devices

Techniques for determining a communication interface of a computer platform. In an embodiment, a power management unit of a computer platform provides to an agent of the platform an indication of a power state. In certain embodiments, the agent determines, based on the indication of the power state, that an interface is expected to be available. The agent may designate information for transmission via the first interface&#x2014;e.g. in lieu of transmitting the information via a second interface which is available prior to the first interface becoming available.

Method, apparatus and system for determining an interface during a power state transition

A configuration memory space is scanned to locate an identification register whose value matches a predetermined value. The identification register identifies the location of a structure within the configuration space. The location of the beginning of the structure is used along with a predetermined (known) offset to determine the address of a desired configuration register.

Method for addressing configuration registers by scanning for a structure in configuration space and adding a known offset

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Folsom, CA, United States of America

Christopher J Lake