International Business Machines Corporation

Christopher J Kiegle

Eric A Foreman

Vladimir P Zolotov

Peter Anton Habitz

Jeffrey G Hemmett

John P Dubuque

Amol Anil Joshi

William John Wright

A statistical single library that includes on-chip variation (OCV) is created for timing and power analysis of a digital chip design. Initially, library values for all cells of a digital chip design, including ranges for environmental and process parameters, are subject to a statistical model to create statistical timing for the ranges of the parameters. A statistical timing tool is applied across the ranges of the parameters to determine statistical corners for delay and input power to a subset of cells. The statistically determined delay and input power to the subset of cells is entered into the statistical single library. Each delay of each statistical corner for the subset of cells is compared with a chip sign-off statistical delay requirement of a test macro.

Statistical single library including on chip variation for rapid timing and power analysis

Growing community of inventors

Jericho, VT, United States of America

Christopher J Kiegle