Ford Motor Company Limited

Intel Corporation

Texas Instruments Corporation

Agilent Technologies, Inc.

Christopher J Kemp

Leland Joseph Spangler

David M Gonzalez

Roger J Cook

Stephen R Tomassetti

Christoph Menzel

Sylvia Jane Budak

Michael C Graf

Kent R Callahan

Jon Tourville

Mark A Streeter

A method and apparatus for reducing charge injection in a FET switch. The switch includes a switch FET and two compensating FETs coupled to an input node. Gate drive signals for the two compensating FETs are generated by a gate drive circuit dependent upon the analog input signal and gate drive signal to the switch FET.

Method and apparatus for reducing charge injection in a FET switch

A way of converting sensed signals to a desirable form of electrical signals is provided that includes providing an input signal to a common input terminal of a sensing block. The way comprises receiving a sensed signal from the sensing block in response to applying the input signal.

Converting sensed signals

A low side line driver (10) includes a slew rate limiter (12) providing current to a pre-charge reference circuit (16). The pre-charge reference circuit (16) generates a constant voltage at the input of a pre-drive circuit (18). Upon a transition to the active state, the pre-charge reference circuit (16) is disabled and current from the slew rate limiter (12) flows to pre-drive circuit (18) which becomes enabled without undue propagation delay or high instantaneous slew rate due to the pre-charge voltage generated by the pre-charge reference circuit (16) before turn on. The pre-drive circuit (18) provides base current to an output driver (22) from a negative voltage created in a charge pump (28). At turn off, an active turn off circuit (26) produces a short output pulse causing rapid discharge of base capacitance of the output driver (22) in order to minimize turn off propagation delay.

Low side line driver

In one embodiment of the present invention, a sensing system utilizing a capacitive sensor includes an integrator which is connected to the sensor and has an operational amplifier and an integrator capacitor, a reference voltage source, a clock generator generating a 3-phase clock, and a number of switches. The switches, during the first phase of the clock connect the sensor capacitors to the reference voltages and cause the capacitors to become charged, and connect the output and the input of the amplifier cand cause the integrator to be shorted. During the second phase, the switches connect the sensor capacitors contained in the capacitive sensor to the ground and disconnect the input of the integrator from the output of the integrator to cause the charges on the sensor capacitor to be transferred to the integrator capacitor. During the third phase, the switches connect the sensor capacitors to the output of the integrator, and the integrator capacitor to the groung so that the charge is transferred from the integrator capacitor to the sensor capacitors of the capacitive sensor. Thus, the output of integrator becomes a scaled version of the difference over the sum of the sensor capacitors. The scale factor can be adjusted by adjusting the reference voltage.

Sampled-data interface circuit for capacitive sensors

A circuit for determining the operability an airbag squib resistor. The circuit includes a current source, the squib resistor to be measured, a first resistor whose resistance is equal to the minimum acceptable resistance of the squib resistor, a second resistor whose resistance is equal to the maximum acceptable resistance of the squib resistor, a voltage-to-current converter, a capacitor, a comparator, and a microprocessor with a counter. A first switch connects the squib resistor and first and second resistors in series. A second switch couples the inputs of the voltage-to-current converter individually across the squib resistor and first and second resistors. As the second switch is coupled to the squib resistor, the first resistor or second resistor, a third switch is opened to initiate charging of the capacitor which is coupled to the output of the voltage-to-current converter. A time measurement is made of the time required for the capacitor to charge to a predetermined threshold voltage. The time measurement is made with the second switch in each of its three states. The time measurements are compared and the squib resistor is deemed inoperative if the time measurement for the squib resistor is not within the range established by the time measurements for the first resistor and the second resistor.

System for detecting operability of an airbag squib resistor

A calibration circuit for a capacitive sensor is disclosed which compensates for any offsets or sensitivity variations of the sensor once the sensor has been calibrated. The circuit uses digital calibration codes determined during calibration. The digital codes are modified and unmodified as inputs to a digital-to-analog converter. The digital-to-analog converter applies the corresponding analog equivalents to the inputs of the sensor in a alternate manner so that the voltages applied to the sensor are balanced around a mirror voltage. The balance around the mirror voltage reduces the electrostatic deflection of the sensor which reduces sensor errors. The output of the sensor is converted to a pulse density signal representative of the output of the sensor.

Calibration circuit for capacitive sensors

A single-point impact sensor has a fully differential capacitive sense element for providing a capacitive difference which is proportional to the acceleration of the vehicle. The capacitive difference is converted into a digital pulse train signal which is pulse density modulated with variations in the capacitance. The pulse density of the pulse train is evaluated according to a hierarchy of counters and timers to determine if it is indicative of an activation worthy event. In one embodiment, a non-volatile programmable memory is provided to control the operation of the impact sensor.

Integrated silicon automotive accelerometer and single-point impact

A circuit (10') and method (50) for digital to analog (D/A) signal conversion. The circuit includes a voltage scaling D/A signal convertor segment (12'), a charge scaling D/A signal convertor segment (14'), and a switch (19) for switching a capacitive load (20') between the voltage and charge scaling D/A signal convertor segments (12',14'). The method includes converting (52,54,56) digital input signals to partial and final analog output signals, and applying (58) a partial analog output signal to the capacitive load (20') before applying (60) the final analog output signal to the capacitive load (20').

Circuit and method for digital to analog signal conversion

A method for mapping the serial 0 and 1 pulses received at a known clock rate from a delta sigma modulator All 0's are generated at the output when no 11 pairs are present in the input signal during the sampled clock periods. A 1 is generated at the output responsive to the input signal and the input signal delayed by one clock period both being 1's when no 00 pairs are present in the input signal during the sampled clock periods. A 1 is generated at the output for each 11 pair not balanced by a 00 pair when 11 and 00 pairs are serially alternating in the input signal during the sampled clock periods. According to this mapping method, the pulse density of 1's in the output signal increases only responsive to an increase in the net number of 11 pairs in the input signal during the sampled clock periods. A circuit for implementing this pulse mapping method is also described.

Pulse density mapping method and circuit for delta sigma modulators

A low voltage detection circuit includes bandgap and differential comparator circuits for generating a first signal proportional to the level of the supply voltage when it exceeds a predetermined range, and an output driver responsive to the first signal for generating an output indication representative of a low or failure condition of the supply voltage.

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Monument, CO, United States of America

Christopher J Kemp