Sun Microsystems, Inc.

Oracle America, Inc.

Other

Mellanox Technologies, Ltd.

Tilera Corporation

Christopher J Jackson

Bjorn Dag Johnsen

Erik E Hagersten

David Brean

Robert Zak

Carl Ramey

Ola Tørudbakken

Mark B Rosenbluth

Mark Donald Hill

David Allen Wood

Aleksandr Guzovskiy

William A Nesheim

Boris Ostrovsky

Anant Agarwal

Ariel Shahar

Ilan Pardo

Matthew Mattina

Erik Hagersten

David M Wentzlaff

Glenn A Dearth

Ian Rudolf Bratt

John R Feehrer

Bruce Edwards

Thomas P Webber

Adi Menachem

Daniel R Cassiday

Richard Schooler

Christopher D Metcalf

Morten Schanke

Liewei Bao

Chyi-Chang Miao

Hans Rygh

Peter Paneah

Patrick Robert Griffin

Monica C Wong-Chan

Kenneth M Steele

Shane Bell

Steinar Forsmo

Rui Xu

Michael Cotsford

Mark R Johnson

Gil Moran

John A Amann

Diane Orf

Hien H Nguyen

Mathew Hostetter

Tzuriel Katoa

Richard Conlin

Pazhani Pillai

Ben Harrison

Matt Orsini

Kevin Joyce

Christine Deignan

Ola Torudrakken

Hans Rygn

One embodiment includes a computing device including peripheral component bus interfaces for connection to a peripheral component bus, a first integrated circuit (IC) chip comprising a processor to initiate a register setup process of the device, a second IC chip including a tile processor including multiple tiles, each tile including at least a processing core configured to generate requests to at least one of the peripheral component bus interfaces, steering configuration registers to store steering configuration data, and steering logic to steer the generated requests responsively to the steering configuration data in the steering configuration registers, and steering register setup circuitry including a multicaster and a register setup memory, wherein the processor is configured to write the steering configuration data to the register setup memory, and the multicaster is configured to multicast the steering configuration data written to the register setup memory to the steering configuration registers of the tiles.

Hardware engine for configuration register setup

A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores. Also disclosed are techniques for implementing hierarchical serial interconnects such as a PCI Express switch topology over a coherent mesh interconnect.

Implementing hierarchical PCI express switch topology over coherent mesh interconnect

A portable vehicle wash system for use during pre-wash and post-wash procedures preferably includes a portable and collapsible free-standing frame capable of may be positioned over an existing vehicle. Such a free-standing frame preferably includes first and second support sections. Each of the first and second support section preferably includes a fluid discharge section, and a plurality of legs integrally formed with the fluid discharge section. Notably, the fluid discharge section of the first support section is isolated from the fluid discharge section of the second support section. A hose is also provided in fluid communication with the free-standing frame. In this manner, the hose may be coupled to an existing water supply source such that water is simultaneously channeled through the free-standing frame and simultaneously dispersed out from the fluid discharge section of each of the first and second support sections.

Portable vehicle wash system and associated method

A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.

Computing in parallel processing environments

One embodiment of the invention provides a method of operating a switch in a communications network. The method includes storing a set of routings for each port in the switch. When a packet is received at a port in the switch, the set of routings corresponding to the port at which the packet was received is accessed. A port from which to forward the packet from the switch is determined in accordance with the set of routings. The packet is then duly forwarded over the network from the port as determined by the routings.

Switching method and apparatus for use in a communications network

A system and method for preventing untrusted nodes from sending or receiving management communications. In an environment such as an InfiniBand communication fabric, a management packet (e.g., a packet traversing virtual lane) is one of four types: 1) Request from a manager node (e.g., Subnet Manager or SM) to an endnode; 2) Reply from an endnode to a request from the manager; 3) Request from an endnode to the manager; and 4) Reply from the manager to the endnode. Switches (and other routing devices) are configured to allow untrusted nodes to send management packets of typesandonly, and to receive management packets of typesandonly. Trusted nodes (e.g., manager nodes, switches) can send and receive all types. Each port of a switch or routing device has an associated indicator reflecting the level of trust afforded the node or switch coupled to the port.

Securing management operations in a communication fabric

A communications node connected to a packet-switched data input/output network, such as an InfiniBand&#xae; network, has a plurality of processing cores on which a subnet management agent may be run. The subnet management agent processes management instructions relating to node configuration. In the invention, the processing core running the subnet management agent may be dynamically changed by one or more of the processing cores in the node. The processing cores may include a host processor, a service processor and an embedded processor, dedicated to a host channel adapter, which provides a communications interface between the network and the node. Various methods may be used to move the subnet management agent, including the use of a register to which one or more of the processing cores may write, and in which is stored an indication of which processing core is currently running the subnet management agent.

Method and apparatus for controlling management agents in a computer system on a packet-switched input/output network

One embodiment of the invention provides a method of handling an incoming packet at a node in a network. The method includes associating at least one source identifier with a link into the node. A packet is then received at the node over the link, and a source identifier is extracted from the received packet. The extracted source identifier is compared with the source identifier(s) associated with the link in order to authenticate the packet.

Method and apparatus for source authentication in a communications network

A system and a method for a first node in a communications network to authenticate a second node. The second node is connected by a communications link to a port of the first node. The method comprises setting a status that the second node is regarded as untrusted by the first node, so that the first node discards selected network management messages received over the communications link from the second node while it is regarded as untrusted. The method further comprises performing an authentication protocol with the second node by receiving at least one message from the second node over the communications link. Such message is discarded if it does not form part of the authentication protocol. The first node then treats the second node as trusted if the authentication protocol is successful, so that the selected network management messages received from the second node are no longer discarded.

Method and apparatus for authenticating nodes in a communications network

One embodiment of the invention provides apparatus and a method for handling an incoming packet at a port in a network. The port belongs to one or more partitions, and at least one service level is associated with each of the partitions. When a packet is received at the port, a partition key and a service level are extracted from the packet. The extracted partition key is used to determine the partition to which the received packet belongs. The service level extracted from the packet is then compared against the service level(s) associated with the determined partition in order to authenticate the packet. In another embodiment, the service level is correlated against a destination identifier from the packet instead of the partition key.

Method and apparatus for verifying service level in a communications network

An apparatus and method for resending a request in a computer system using a delay value is provided. In response to receiving a request, a target device in a computer system may detect that it is temporarily unable to process the request. The target device can send a response to the sending device to indicate that it is temporarily unavailable. The response can include a delay value that can provide a hint to the sending device as to when to resend the request. The target device may generate the delay value according to the type of condition that is causing it to be temporarily unavailable. The delay value may be generated according to a static heuristic or a dynamic algorithm based on previous temporarily unavailable conditions. The delay value may also be used by an error recovery mechanism where a sending device exceeds a retry limit for a particular request.

System and method for enhancing communication between devices in a computer system

A method and device for off-loading from an application program the calculation of a data-integrity-checking value for specified data in a computer system. The data may be included in a message together with the integrity-checking value or may be in a portion of a memory window for direct memory access. The method includes communicating a selected data-integrity-checking scheme from a specified set of schemes to another processor to off-load calculation of the data-integrity-checking value. A related method associates a message to be received with a data-integrity-checking scheme, so that a receiving processor can calculate the data-integrity-checking value and transmit both the value and the message to another processor.

Method and device for off-loading message digest calculations

A method and device for dynamically targeting interrupts in a computer system. When an operation is initiated, an identifier for the initiator of the operation is stored along with an operation identifier. When an operation completes or needs processor attention due to an error condition or otherwise, the processor or node to interrupt is determined based on the stored indication of the initiator of the operation. An interrupt target data structure may be provided that contains associations between sources that initiate operations and those targets that can service interrupts. If a target scheduled to field an interrupt becomes unavailable, the interrupt can be retargeted to another processor or node by reloading an entry in the interrupt target data structure.

Method and device for dynamic interrupt target selection

A method and mechanism for annotating a transaction stream. A processing unit is configured to generate annotation transactions which are inserted into a transaction stream. The transaction stream, including the annotations, are subsequently observed by a trace unit for debug or other analysis. In one embodiment, a processing unit includes a trace address register and an annotation enable bit. The trace address register is configured to store an address corresponding to a trace unit and the enable bit is configured to indicate whether annotation transactions are to be generated. Annotation instructions are added to operating system or user code at locations where annotations are desired. In one embodiment, annotation transactions correspond to transaction types which are not unique to annotation transactions. In one embodiment, an annotation instruction includes a reference to the trace address register which contains the address of the trace unit. Upon detecting the annotation instruction, and detecting annotations are enabled, the processing unit generates an annotation transaction addressed to the trace unit. In one embodiment, annotation transactions may be used to indicate context switches, processor mode changes, timestamps, or address translation information.

Annotations for transaction tracing

A system for permitting remote user access to regions of memory that have been exported for remote direct memory access purposes. The system supports dynamically changing access privileges to remote users without requiring intervention from an operating system. The system may include a memory region table and a memory window table for supporting address translations. Entries in the memory window table may include a region remote access key and a window remote access key. The memory region table may include fields for a physical address, an access value, a protection domain value, and a length of memory region.

System for accessing a region of memory using remote address translation and using a memory window table and a memory region table

Growing community of inventors

Westford, MA, United States of America

Christopher J Jackson