Xilinx, Inc.

Christopher J Borrelli

Alan C Wong

Yohan Usthavia Frans

Caleb S Leung

Kun-Yung Chang

Geoffrey Zhang

Yu Xu

Edward Kihyen Lee

Glenn A Baxter

Hongtao Zhang

Zhaoyin D Wu

Michael O Jenkins

Winson Lin

Loren Jones

Seu Wah Low

Hong Sik Ahn

Cheng-Hsiang Hsieh

Parag Upadhyaya

Sarosh Azad

Paul M Hartke

Robert M Ondris

Chuen-Huei Chou

Murtuza Z Cutleriwala

Sai Lalith Chaitanya Ambatipudi

Tianyu Fang

Ivan O Madrigal

Using 'in-situ on-die time-domain reflectometry (TDR)' with data signal paths of integrated circuits, printed circuit boards, and data processing equipment and systems allows testing, verification and troubleshooting of data channel signal path impedance variations including the package, escape routing, socket, board, and cable/connectors provides fast characterization thereof. Operation of “in-situ on-die TDR” uses existing analog-to-digital converter (ADC) and data transmitter (TX) drivers of an integrated circuit to act as a TDR sampling head by performing a user interface-based TDR sampling with a step-waveform generated by an integrated circuit TX driver. Then sampling the step-waveform with the ADC of the integrated circuit using spline interpolation to obtain the over-sampled waveform. Once the sampled step-waveform is obtained, the TDR profile of the sampled data channels may be calculated. Large amounts of impedance variation data may thus be collected during either integrated circuit manufacturer or customer-built data communications channel testing.

Equipment design and testing using in-situ on-die time-domain reflectometry

A method relates generally to comparison of a communications system modelled with a behavioral model and implemented with a circuit realization. In this method, operation of the communications system is simulated with the behavioral model on a computing device to obtain a first pulse response. The simulating includes first equalizing first data with a first equalizer of the behavioral model to obtain the first pulse response. The circuit realization is operated to obtain a second pulse response. The operating includes: second equalizing second data corresponding to the first data with a second equalizer of the circuit realization to obtain the second pulse response. The second pulse response from the circuit realization is loaded to memory of the computing device. The first pulse is loaded to the memory of the computing device. The first pulse response and the second pulse response are compared with one another by the computing device.

Method and system for correlation of a behavioral model to a circuit realization for a communications system

Apparatus and associated methods relating to reducing lock time include pre-calibrating and storing phase-locked loop (PLL) and/or injection-locked oscillator (ILO) adaptation values during startup and loading the pre-calibrated values during rate change. In an illustrative example, an integrated circuit may include a controllable frequency circuit operable at frequencies within each of a plurality of frequency bands. A data store may store operational settings associated with each frequency of the plurality of frequency bands. A state machine may be coupled to the controllable frequency circuit and the data store configured to select a predetermined frequency band in response to a command signal, retrieve, from the data store, operational settings associated with the predetermined frequency band, and, apply the retrieved operational settings to the controllable frequency circuit. With the pre-calibration, PLL and/or ILO lock times during rate change in a multi-rate serializer/deserializer (SERDES) link may be advantageously reduced.

Apparatus and method to reduce lock time via frequency band calibration

A circuit includes an AGC adaptation circuit configured to receive a first signal generated based on an AGC output signal from an AGC circuit. The AGC circuit applies an AGC gain to an AGC input signal to generate the AGC output signal. The AGC adaptation circuit determines an observed value of the first signal, and determines a AGC adaptation step size based on the observed value and a predetermined target value associated with the first signal. The AGC adaptation circuit provides a second signal to adjust the AGC gain of the AGC circuit using the AGC adaptation step size.

System and method for automatic gain control adaptation

An example method of clock and data recovery in a receiver includes generating data samples and crossing samples of a received signal based on a data clock signal and a crossing clock signal, respectively, which are derived from a sampling clock signal; adjusting a phase of the sampling clock signal using a clock and data recovery (CDR) circuit based on the data samples and the crossing samples; adjusting relative phase between the data clock signal and the crossing clock signal from a first phase difference to a second phase difference that is less than ninety degrees; and reverting the relative phase between the data clock signal and the crossing clock signal to the first phase difference after a threshold time period.

Temporal change in data-crossing clock phase difference to resolve meta-stability in a clock and data recovery circuit

An example method of clock and data recovery in a receiver includes generating data samples and crossing samples of a received signal based on a data phase and a crossing phase, respectively, of a sampling clock supplied by a phase interpolator in the receiver; generating a phase detect result signal in response to phase detection of the data samples and the crossing samples; filtering the phase detect result signal to generate a phase interpolator code, the phase interpolator generating the sampling clock based on the phase interpolator code; determining an average phase detect result from the phase detect result signal; and adjusting the phase interpolator code in response to the average phase detect result being less than a threshold value.

Resolving meta-stability in a clock and data recovery circuit

An example method of performing an eye-scan in a receiver includes: generating digital samples from an analog signal input to the receiver based on a sampling clock, the sampling clock phase-shifted with respect to a reference clock based on a phase interpolator (PI) code; equalizing the digital samples based on first equalization parameters of a plurality of equalization parameters of the receiver; adapting the plurality of equalization parameters and performing clock recovery based on the digital samples to generate the PI code; and performing a plurality of cycles of locking the plurality of equalization parameters, suspending phase detection in the clock recovery, offsetting the PI code, collecting an output of the receiver, resuming the phase detection in the clock recovery, and unlocking the equalization parameters to perform the eye scan.

Built-in eye scan for ADC-based receiver

A method relates generally to a receiver. In such a method, a check of a clock and data recovery block of the receiver for a metastable state is performed. A phase input to a phase interpolator of the receiver is changed to cause the clock and data recovery block of the receiver to exit the metastable state within a time limit. To check for the metastable state, a phase difference in received data is determined, and the phase difference is determined to be less than a threshold for the clock and data recovery block being in the metastable state.

Fast locking CDR for burst mode

An apparatus relating generally to a transmitter-side of a transceiver or a transmitter used to provide a clock signal is disclosed. In this apparatus, a first signal source is to provide a first periodic signal. A second signal source is to provide a second periodic signal. A first multiplexer is coupled to receive the first periodic signal and the second periodic signal to provide a selected one thereof as a first selected output. A phase interpolator is coupled to the first multiplexer to receive the first selected output. The phase interpolator includes a second multiplexer. The second multiplexer is coupled to receive the first selected output and a phase-interpolated version of the first selected output to output a selected one thereof as a second selected output. A divider is coupled to the second multiplexer to receive the second selected output to provide the clock signal.

Transceiver for providing a clock signal

A receiver in an integrated circuit device is described. The circuit comprises a receiver having a clock and data recovery circuit coupled to receive data signals modulated with a transmitter clock signal; and a clock generator coupled to receive an output of the clock and data recovery circuit, the clock generator providing a modulated reference clock to the receiver, based upon a reference clock signal which is independent of the transmitter clock signal; wherein the modulated reference clock provided to the receiver is synchronized with the transmitter clock signal. A method of receiving data in an integrated circuit is also described.

Circuits for and methods of implementing a receiver in an integrated circuit device

Circuits and methods are provided for estimating a latency through a FIFO buffer. A first detector detects first instances of a pattern in first data values serially written to a write port of the FIFO buffer. A second detector detects second instances of the pattern in second data values serially read from a read port of the FIFO buffer. The second data values are the first data values delayed by the latency through the FIFO buffer. A counter counts a count of active transitions of a sample clock signal. The counter starts on each detected first instance and stops on each detected second instances. The count provides an estimate of the latency of the FIFO buffer.

Circuit for estimating latency through a FIFO buffer

Method and apparatus for communicating data between a network transceiver and memory circuitry is described. In one example, a transmit peripheral includes a streaming interface configured to receive a communication sequence having data read from the memory circuitry. A receive peripheral includes a streaming interface configured to transmit a communication sequence having data to be written to the memory circuitry. Media access control (MAC) circuitry is configured to transmit the data read from the memory circuitry to the network transceiver, and receive the data to be written to the memory circuitry from the network transceiver.

Method and apparatus for communicating data between a network transceiver and memory circuitry

Method and apparatus for controlling direct access to memory circuitry by a device is described. In one example, a streaming interface is configured to transmit and receive a communication sequence to and from the device. Control logic is configured to implement a plurality of direct memory access (DMA) engines. The DMA engines are configured to read and write data to and from the memory circuitry. A set of registers is configured to store control data for the plurality of DMA engines.

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Los Gatos, CA, United States of America

Christopher J Borrelli