International Business Machines Corporation

Christopher J Berry

Sourav Saha

Lakshmi Narasimha Reddy

Ricardo H Nigaglioni

Alan P Wagstaff

Patrick James Meaney

Michael H Wood

Shyam Ramji

Haifeng Qian

Randall J Darden

Jose Luis Neves

Pinaki Chakrabarti

Kaustav Guha

Eddy St Juste

Michael F Fee

Howard Harold Smith

Sridhar H Rangarajan

Jesse Peter Surprise

Jonathan Yang Chen

Joseph J Palumbo

George Antony

Chris Aaron Cavitt

Vinay K Singh

Richard P Underwood

Paul Gerard Villarrubia

Mark Carl Hampton

Adam P Matheny

Matthew Mantell Ziegler

Lawrence D Curley

Michael Alexander Bowen

Timothy A Schell

Arjen Alexander Mets

Gerald Strevig, Iii

Charudhattan Nagarajan

Yiu-Hing Chan

Frank Malgioglio

Amanda Christine Venton

Adam R Jatkowski

Hameedbasha Shaik

Ajith Kumar M Chandrasekaran

Matthew D Affeldt

Joseph N Kozhaya

Jerome J Cuomo

Gi-Joon Nam

Gary A Van Huben

Gustavo Enrique Tellez

Robert Alan Philhower

Diana Lynn Orf

C Richard Guarnieri

Charlie Chornglii Hwang

David Allan Webber

Jinwook Jung

Ofer Geva

Michael R Scheuermann

David L Rude

Daniel Richard Menard

Shawn Kollesar

William J Scarpero, Jr

Christopher Carney

Dennis S Yee

Jose Luis Pontes Correia Neves

Travis Wellington Pouarz

David W Lewis

Eric Chien Lai

Amit Amos Atias

Chaobo Li

Peter Milton Nasveschuk

Asaf Regev

Dina Hamid

Susan R Sanicky

Jose Luis Pontes Correla Neves

Adam R Jalkowski

Ryan M Nett

Sean Salisbury

A method for curing antenna violations on an integrated circuit that includes multiple levels includes: obtaining a design of a circuit, the design including a first element connected to first device and a second element connected to one or more second devices, wherein the first and second elements both receive a common signal; determining that an antenna violation exists in on the first element at a first level of the multiple levels; and modifying the design of the circuit to add a connected between the first element and the second element at the first layer or at a layer below the first layer.

Method to cure antenna violations in clock network using jumpers

A method for distributing deep trench (DT) capacitance in an integrated circuit (IC) design is provided. The method includes forming a placement block that includes blockages defining openings in interstitial regions among the blockages, superimposing the placement block over the IC design and providing distributed DT capacitance to the IC design. The providing of the distributed DT capacitance includes adding DT capacitance cells through the openings to portions of the IC design where there are no reserved blocks.

Deep trench capacitor distribution

A computer-implemented method, computer program product, and computing system is provided for scoping searches within a website. In an implementation, a method may receiving a search request. The method may also include identifying a location of a search scoping feature within a website hierarchy. The method may further include setting a search scope relative to the search request based on, at least in part, the location of the search scoping feature.

Scoping searches within websites

For each of a plurality of source-sink pairs, a corresponding interconnect layer is selected having a reach length which permits propagation of a required signal within a required sink cycle delay. For a first clock cycle, a movable region for a first latch is located as a first plurality of overlapped regions one reach length from a source and the required sink cycle delay number of reach lengths from each one of the sinks; and the first plurality of overlapped regions is represented as nodes on a first cycle level of a topology search graph. Analogous actions are carried out for a second clock cycle of the required sink cycle delay. A latch tree is created based on the topology search graph, wherein a required number of latches is minimized, and at each of the cycle levels, all sinks of source nodes selected at a previous level are covered.

Multi-cycle latch tree synthesis

Methods, systems and computer program products for improved metal fill shape removal from selected nets are provided. Aspects include determining a first set and second set of timing characteristics of a first and second circuit design, respectively. The first circuit design does not include metal fill shapes around a plurality of nets, whereas the second circuit design does include metal fill shapes around a plurality of nets. Aspects also include identifying a set of candidate nets based on a comparison of the first set of timing characteristics to the second set of timing characteristics. The set of candidate nets are nets that are candidates for metal fill shape removal. Aspects include generating a third circuit design by removing one or more metal fill shapes positioned around each net of the set of candidate nets that are positioned within a radius of removal.

Metal fill shape removal from selected nets

A data processing system to implement wiring/silicon blockages via parameterized cells (pCells) includes a front end-of-line placement/blockage (FEOL P/B) controller to generate a placement blockage based on an input parameter corresponding to a physical design of an integrated circuit (IC). The FEOL P/B outputs a placement blockage parameter that is stored in a wire track allocation database to indicate the placement blockage. A back end-of-line wiring track (BEOL WT) controller generates a wire track blockage of the IC. A BEOL power track (BEOL PT) controller generates a metal blockage within the wire track blockage. A combination of the metal blockage and the wire track blockage defines a parent-child contract to enable concurrent physical design of the IC without creating shorts and overlaps in a child block of the IC.

Data processing system to implement wiring/silicon blockages via parameterized cells

Embodiments relate to managing layer promotion of interconnects in the routing phase of integrated circuit design. An aspect includes a system to manage layer promotion in a routing phase of integrated circuit design. The system includes a memory device to store instructions, and a processor to execute the instructions to identify a set of candidate interconnects for layer promotion, score and sort the set of candidate interconnects according to a respective score to thereby establish a respective rank, assess routing demand and resource availability based on layer promotion of the set of candidate interconnects, and manage the set of candidate interconnects based on the respective rank and the resource availability, the processor assessing the routing demand and resource availability and managing the set of candidate interconnects iteratively, wherein the processor, in at least one iteration, generates a second set of candidate interconnects by reducing the set of candidate interconnects.

Congestion aware layer promotion

A system and a computer implemented method for interior pinning in a macro block of an integrated circuit are provided. The method includes receiving child level information of the macro block including at least a location of a logic leaflet, receiving parent level information including at least edge direction information for pin connection and routing resource values of each slot of the macro block at each metal layer, and selecting a pin location based on the child level information and the parent level information.

Hierarchically aware interior pinning for large synthesis blocks

A method and system to identify a region of a design block of an integrated circuit for redesign are described. The method includes dividing the design block into grids, each of the grids including a corresponding number of logic elements. The method also includes filtering each of the grids based on a specified criteria, the filtering including determining a number (B) of the corresponding logic elements among a total number (A) of the logic elements in each grid that meet the specified criteria. The region is a set of two or more of the grids based on a result of the filtering.

Critical region identification

A first open path in a microprocessor design is identified. At least one modification to a design of that first open path is simulated. An updated arrival time at a pin is calculated based on the simulated modification or modifications. An updated path time is then calculated based on the updated arrival time.

Simulation of modifications to microprocessor design

A computer-implemented method of performing physical synthesis in a chip design process using hierarchical wire-pin co-optimization, a system, and a computer program product are described. Aspects include providing an indication of candidate pins among a plurality of pins of a plurality of macros that may be moved, and providing constraints on a range of movement of one or more of the plurality of pins. Aspects also include performing macro-level physical synthesis at each of the plurality of macros based on the candidate pins and the constraints to generate pin locations and timing results.

Constraint-driven pin optimization for hierarchical design convergence

Embodiments relate to cross-hierarchy interconnect adjustment. An aspect includes receiving chip layout data corresponding to a chip design, wherein a first portion of a metal stack of the chip design is assigned to a first hierarchy and a second portion of the metal stack is assigned to a second hierarchy based on a contract between the first and second hierarchy. Another aspect includes determining an unused portion of the first portion of the metal stack. Another aspect includes moving an interconnect of the second hierarchy from the second portion of the metal stack that is assigned to the second hierarchy to the unused portion of the first portion of the metal stack in the chip layout data. Another aspect includes performing power recovery on the chip layout data after moving the interconnect based on an amount of slack margin generated in the chip design by the moving of the interconnect.

Cross-hierarchy interconnect adjustment for power recovery

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Christopher J Berry