Abb Research Ltd.

Acreo Ab

Asea Brown Boveri Ab

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Christopher Ian Harris

Mietek Bakowski

Ulf Gustafsson

Andrei Konstantinov

Erik Janzen

Bo Bijlenga

Lennart Zdansky

Susan Savage

Kurt Rottner

Mietek Bakowsky

Mats Andersson

Willy Hermansson

Adolf Schoner

Andrey Konstantinov

Lennart Ramberg

Thomas H&ouml;rman

Nils Lundberg

Erik Danielsson

Stefan Karlsson

Mikael Ostling

Jan Szmidt

Christian Ad&aring;s

Fanny Dahlquist

A semiconductor device comprises at least one first semiconductor layer ( ) and a second layer ( ) applied on at least a surface portion of the first layer for protecting the device. The protecting layer is of a second material having a larger energy gap between the valence band and the conduction band than a first material forming said first layer. The second material has at least in one portion of said protecting layer a nano-crystalline and amorphous structure by being composed of crystalline gains with a size less than 100 nm and a resistivity at room temperature exceeding 1&times;10 &OHgr;cm.

Protective layer for a semiconductor device

The invention relates to a method for selective etching of SiC, the etching being carried out by applying a positive potential to a layer (,) of p-type SiC being in contact with an etching solution containing fluorine ions and having an oxidising effect on SiC. The invention also relates to a method for producing a SiC micro structure having free hanging parts (i.e. diaphragm, cantilever or beam) on a SiC-substrate, a method for producing a MEMS device of SiC having a free hanging structure, and a method for producing a piezo-resistive pressure sensor comprising the step of applying a positive potential to a layer (,) of p-type SiC being in contact with an etching solution containing fluorine ions and having an oxidising effect on SiC.

Method of producing a semiconductor device of SiC

A field effect transistor of SiC for high temperature application has the source region layer (,), the drain region layer (,) and the channel region layer (,) vertically separated from a front surface (,), where a gate electrode (,) is arranged, for reducing the electric field at said surface in operation of the transistor and in the case of operation as a gas sensor permitting all electrodes except for the gate electrode to be protected from the atmosphere.

Field effect transistor of SiC for high temperature application, use of such a transistor and a method for production thereof

In a high power IMPATT ( Impact Avalanche Transit Time) diode for generating high frequency signals two electrodes, anode (,) and cathode (,), are arranged with a semiconductor layer therebetween. Said semiconductor layer comprises a drift layer (,) for transport of charge carriers between the electrodes. The semiconductor layer is made of crystalline SiC and it is provided with means (,) adapted to locally increase the electric field in the drift layer substantially with respect to the average electric field therein for generating an avalanche breakdown at a considerably lower voltage across the electrodes than would the electric field be substantially constant across the entire drift layer.

High power impatt diode

A transistor of SiC having a drain and a highly doped substrate layer is formed on the drain. A highly n type buffer layer may optionally be formed on the substrate layer. A low doped n-type drift layer, a p-type base layer, a high doped n-type source region layer and a source are formed on the substrate layer. An insulating layer with a gate electrode is arranged on top of the base layer and extends substantially laterally from at least the source region layer to a n-type layer. When a voltage is applied to the gate electrode, a conducting inversion channel is formed extending substantially laterally in the base layer at an interface of the p-type base layer and the insulating layer. The p-type base layer is low doped in a region next to the interface to the insulating layer at which the inversion channel is formed and highly doped in a region thereunder next to the drift layer.

Semiconductor device having high channel mobility and a high breakdown

A lateral field effect transistor of SiC for high switching frequencies comprises a source region layer (5) and a drain region layer (6) laterally spaced and highly doped n-type, an n-type channel layer (4) extending laterally and interconnecting the source region layer and the drain region layer for conducting a current between these layers in the on-state of the transistor, and a gate electrode (9) arranged to control the channel layer to be conducting or blocking through varying the potential applied to the gate electrode. A highly doped p-type base layer (12) is arranged next to the channel layer at least partially overlapping the gate electrode and being at a lateral distance to the drain region layer. The base layer is shorted to the source region layer.

Lateral field effect transistor of SiC, a method for production thereof

A Schottky diode of SiC has a substrate layer, a drift layer and emitter layer regions formed in the drift layer. A metal layer makes an ohmic contact to the emitter layer regions and Schottky contact to the drift layer. A depletion of the drift layer region between two adjacent emitter layer regions is allowed in the blocking state of the diode making the two adjacent p-type emitter layer regions form a continuous depleted region therebetween in this state.

Schottky diode of SiC and a method for production thereof

A method for introducing an impurity dopant into a semiconductor layer of SiC is provided. Ions are implanted into the semiconductor layer so that a near surface of the semiconductor layer becomes doped and amorphous. The semiconductor layer is then annealed at a temperature so that the dopant diffuses into a non-implanted sublayer of the semiconductor layer below the near surface layer.

Method for introduction of an impurity dopant in SiC, a semiconductor

A semiconductor device of SiC is adapted to hold high voltages in the blocking state thereof. The device comprises two parts (1, 2) each comprising one or more semiconductor layers of SiC and connected in series between two opposite terminals of the device, namely a sub-semiconductor device (1) able to withstand only low voltages in the blocking state thereof and a voltage-limiting part (2) able to withstand high voltages in the blocking state of the device and adapted to protect said sub-semiconductor device by taking a major part of the voltage over the device in the blocking state thereof.

Semiconductor device of SiC having an insulated gate and buried grid

A semiconductor device comprises at least one semiconductor layer of SiC and a layer of a refractory metal nitride separated by an insulating layer located next to the SiC layer of SiO.sub.2. The insulating layer comprises two sub layers, namely a first sub layer of SiO.sub.2 next to the SiC layer and a second sub layer of Si.sub.3 N.sub.4 located between the first sub layer and the metal nitride layer.

Semiconductor device of SiC with insulating layer and a refractory metal

A semiconductor component, which comprises a pn junction, where both the p-conducting and the n-conducting layers of the pn junction constitute doped silicon carbide layers and where the edge of at least one of the conducting layers of the pn junction, exhibits a stepwise or uniformly decreasing total charge or effective surface charge density from the initial value at the defined working junction to a zero or almost zero total charge at the outermost edge of the junction following a radial direction from the central part of the junction towards the outermost edge.

SiC Semiconductor device comprising a pn Junction with a voltage

A semiconductor component comprises a pn junction in which both the p-conducting and the n-conducting layers of the pn junction are doped silicon carbide layers and the edge of at least one of the conducting layers of the pn junction exhibits a stepwise or uniformly decreasing total charge or effective surface charge density from the initial value at the defined working junction to a zero or almost zero total charge at the outermost edge of the junction following a radial direction from the central part of the junction towards its outermost edge.

SiC semiconductor device comprising a pn junction with a voltage

A semiconductor device of planar structure, comprises a pn junction, formed of a first type conducting layer and on top thereof a second type conducting layer, both layers of doped silicon carbide, the edge of the second of the layers being provided with an edge termination (JTE), enclosing stepwise or continuously decreasing effective sheet charge density towards the outer border of the termination, wherein the pn junction and its JTE are covered by a doped or undoped SiC third layer.

SiC semiconductor device comprising a pn junction

A field controlled semiconductor device of SiC comprises superimposed in the order mentioned at least a drain (12), a highly doped substrate layer (1) and a low doped n-type drift layer (2). It has also a highly doped n-type source region layer (6) and a source (11) connected thereto. A doped channel region layer (4) connects the source region layer to the drift layer, and a current is intended to flow therethrough when the device is in an on-state. The device has also a gate electrode (9). The channel region layer has a substantially lateral extension and is formed by a low doped n-type layer (4). The gate electrode (9) is arranged to influence the channel region layer from above for giving a conducting channel (17) created therein from the source region layer to the drift layer a substantially lateral extension.

Field controlled semiconductor device of SiC and a method for production

An IGBT comprises a drain, a highly doped p-type substrate layer, a highly doped n-type buffer layer, a drift layer, a p-type base layer, a highly doped n-type source region layer and a source electrode. A trench is etched in the base layer and an insulating layer with a gate electrode thereon is arranged on the base layer from the source region layer to the drift layer for the creation of a conducting inversion channel there. A contact portion is provided vertically separated from the source region layer and has the source electrode applied thereon for collecting holes injected from the substrate layer to the drift layer at a vertical distance from the source region layer.

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Sollentuna, Sweden

Christopher Ian Harris