Amdahl Corporation

Rise Technology Company

Christopher I Norrie

Peter K Yu

Allan J Zmyslowski

Stephen J Rawlinson

Dzung X Tran

Carolee V Newcomb

Carolee N Newcomb

A novel method and apparatus is disclosed for locating the first most, or least, significant set bit in a bit-string. The present invention breaks down the bit-string into a plurality of shorter sub-strings so that boolean operations can be performed directly to the shorter sub-strings for determining the location of the most/least significant set bit. Furthermore, this method can be repeatedly used to reduce the length of the shorter sub-string after the most/least significant sub-string is located. Particularly, this method of repeatedly dividing the bit-string greatly increases the speed of locating the set bit.

Efficient bit scan mechanism

A pipelined computer which process operand data through a sequence of D,A,T,B,X and W stages includes a sidetrack queue. Data which exits the B stage prematurely, before the X stage is ready to immediately process such data, is held over in the sidetrack queue and presented to the X stage at a later time. The sidetracking mechanism is used to speed processing of rate-variable operand-consuming instructions such as the EDIT and EDMK commands.

Expedited execution of pipelined command having self-ordering operand

A mapping system for mapping a plurality of two byte operation code series into a control store where in each two byte operation code the first byte identifies the series in which that two byte operation code is included and the second byte identifies that specific operation code within the identified series, the mapping system comprising a first register for storing the first and second bytes of a two byte operation codes, a first control store for storing control word for the two byte operation codes, a first means for generating, from the first and second bytes stored in the first register, a first control store address for the first control store thereby providing access to the control word for processing the two byte operation code store in the first register and a second means for generating, from the first and second bytes stored in the first register, a first signal when an invalid two byte operation code has been stored in the first register for processing, the first signal invalidating the processing of the two byte operation code stored in the first register including any processing of the control word accessed by the first control store in response to the first control store address generated by the first means.

System for checking the validity of two byte operation code by mapping

An error recovery system used in a pipeline architecture type computer system for recovering from an error in a control word for an instruction without interrupting the sequence of processing control words by the computer system. The computer system processes instructions in a sequence of overlapping FLOWs where each FLOW is comprised of a sequence of cycles. An instruction control word is processed in each cycle of each FLOW. The error recovery system comprises a first storage for storing, for a given cycle of a FLOW, all the control words for all the instructions, a second storage for storing a control word read from the first storage and an error recovery logic for detecting an error in the control word read from the first storage and stored in the second storage and for correcting the error in the control word in the first and second storage.

Growing community of inventors

San Jose, CA, United States of America

Christopher I Norrie