Rambus Inc.

Inphi Corporation

Alcatel

Alcatel Lucent

Alcatel Internetworking, Inc.

Xylan Corporation

Rambus Lnc.

Christopher Haywood

Evan Lawrence Erickson

David T Wang

Frederick Abbott Ware

Shih-ho Wu

Chao Xu

Geoffrey C Stone

Fouad G Tamer

John Eric Linstadt

Steven Cameron Woo

Gopal Raghavan

Mark D Kellam

Wai King

Craig Edward Hampel

Nirmal Raj Saxena

Michael J De La Garrigue

Eric Deshan McDonald

David Wang

Many error correction schemes fail to correct for double-bit errors and a module must be replaced when these double-bit errors occur repeatedly at the same address. This helps prevent data corruption. In an embodiment, the addresses for one of the memory devices exhibiting a single-bit error (but not the other also exhibiting a single bit error) is transformed before the internal memory arrays are accessed. This has the effect of moving one of the error prone memory cells to a different external (to the module) address such that there is only one error prone bit that is accessed by the previously double-bit error prone address. Thus, a double-bit error at the original address is remapped into two correctable single-bit errors that are at different addresses.

Error remapping

An apparatus and method for low page overhead recompression. In one embodiment a memory buffer integrated circuit (IC) device is disclosed that includes a first circuit configured to independently compress equally sized portions of a page of data, and a second circuit configured to store the compressed data portions at respective addresses in memory. The memory buffer IC device also includes a third circuit configured to store a page table comprising an entry with information related to the respective memory addresses.

Low overhead page recompression

A serial data buffer integrated circuit comprises unidirectional host-side input and output ports, and unidirectional memory-side input and output ports. Scheduling logic generates memory device commands for writing to and reading from a memory device based on a set of host-side input packets received from a memory controller. A unidirectional serial host side input port receives host-side input packets from the memory controller. A unidirectional serial memory side output port transmits the memory device commands and the write data to the memory device based on the scheduled timing. A unidirectional serial memory side input port receives read data from the memory device in response to a read command, and a unidirectional serial host side output port transmits the read data to the memory controller within the timing constraints of the memory device.

Data buffer for memory devices with unidirectional ports

An integrated circuit device includes a first memory to support address translation between local addresses and fabric addresses and a processing circuit, operatively coupled to the first memory. The processing circuit allocates, on a dynamic basis as a donor, a portion of first local memory of a local server as first far memory for access for a first remote server, or as a requester receives allocation of second far memory from the first remote server or a second remote server for access by the local server. The processing circuit bridges the access by the first remote server to the allocated portion of first local memory as the first far memory, through the fabric addresses and the address translation supported by the first memory, or bridge the access by the local server to the second far memory, through the address translation supported by the first memory, and the fabric addresses.

Far memory allocator for data center stranded memory

A cascaded memory system includes a memory module having a primary interface coupled to a memory controller via a first communication channel and a secondary interface coupled to a second memory module via a second communication channel. The first memory module buffers and repeats signals received on the primary and secondary interfaces to enable communications between the memory controller and the secondary memory module.

Cascaded memory system

A buffer integrated circuit (IC) chip is disclosed. The buffer IC chip includes host interface circuitry to receive a request from at least one host. The request includes at least one command to perform a memory compression operation on first uncompressed data that is stored in a first memory region. Compression circuitry, in response to the at least one command, compresses the first uncompressed data to first compressed data. The first compressed data is transferred to a second memory region.

Compressed memory buffer device

A buffer/interface device of a memory node reads a block of data (e.g., page). As each unit of data (e.g., cache line sized) of the block is read, it is compared against one or more predefined patterns (e.g., all 0's, all 1's, etc.). If the block (page) is only storing one of the predefined patterns, a flag in the page table entry for the block is set to indicate the block is only storing one of the predefined patterns. The physical memory the block was occupying may then be deallocated so other data may be stored using those physical memory addresses.

Compression via deallocation

A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.

Memory buffer with data scrambling and error correction

The creation, maintenance, and accessing of page tables is done by a virtual machine monitor running on a computing system rather than the guest operating systems. This allows page table walks to be completed in fewer memory accesses when compared to the guest operating system's maintenance of the page tables. In addition, the virtual machine monitor may utilize additional resources to offload page table access and maintenance functions from the CPU to another device, such as a page table management device or page table management node. Offloading some or all page table access and maintenance functions to a specialized device or node enables the CPU to perform other tasks during page table walks and/or other page table maintenance functions.

Page table manager

In a modular memory system, a memory control component, first and second memory sockets and data buffer components are all mounted to the printed circuit board. The first and second memory sockets have electrical contacts to electrically engage counterpart electrical contacts of memory modules to be inserted therein, and each of the data buffer components includes a primary data interface electrically coupled to the memory control component, and first and second secondary data interfaces electrically coupled to subsets of the electrical contacts within the first and second memory sockets, respectively.

Off-module data buffer

Memory pages are background-relocated from a low-latency local operating memory of a server computer to a higher-latency memory installation that enables high-resolution access monitoring and thus access-demand differentiation among the relocated memory pages. Higher access-demand memory pages are background-restored to the low-latency operating memory, while lower access-demand pages are maintained in the higher latency memory installation and yet-lower access-demand pages are optionally moved to yet higher-latency memory installation.

Heterogenous-latency memory optimization

A hybrid volatile/non-volatile memory module employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM). A module controller prioritizes accesses to the DRAM cache for improved speed performance and to minimize programming cycles to the NVM. Data is first written to the DRAM cache where it can be accessed (written to and read from) without the aid of the NVM. Data is only written to the NVM when that data is evicted from the DRAM cache to make room for additional data. Mapping tables relating NVM addresses to physical addresses are distributed throughout the DRAM cache using cache line bits that are not used for data.

Nonvolatile physical memory with DRAM cache

A memory system includes a memory controller, a plurality of serial data buffers, and a plurality of memory devices. The memory controller issues packetized commands and data to the serial data buffers. The serial data buffers each apply a different remapping function to remap an input command address in the packetized commands to respective remapped memory addresses that are different for each serial data buffer. The serial data buffers then issue commands to the memory devices using the remapped addresses. The remapping functions may be designed to mitigate row hammer effects. The serial data buffers may furthermore apply transformations to read and write data to facilitate encryption and decryption.

Data buffer for memory devices with memory address remapping

The present invention is directed to computer storage systems and methods thereof. In an embodiment, a memory system comprises a controller module, a nonvolatile memory, and a volatile memory. The controller module operates according to a command and operation table. The command and operation table can be updated to change the way controller module operates. When the command and operation table is updated, the updated table is stored at a predefined location of the nonvolatile memory. There are other embodiments as well.

Growing community of inventors

Thousand Oaks, CA, United States of America

Christopher Haywood