Cree Gmbh

Cree Sweden Ab

Christopher Harris

Andrei Konstantinov

Cem Basceri

Thomas Gehrke

Mietek Bakowski

T Warren Weeks, Jr

Kent Bertilsson

Jan-Olov Svederg

Raymond Sydney Pengelly

Cengiz Balkas

Mats Andersson

Elif Berkman

Bertilsson Kent

Andrei c/o Saraby Kunstantinov

Ulf Gustafsson

A trench metal oxide semiconductor field effect transistor or UMOSFET, includes a buried region that extends beneath the trench and beyond a corner of the trench. The buried region is tied to a source potential of the UMOSFET, and splits the potential realized across the structure. This effectively shields the electric field from the corners of the trench to reduce gate oxide stress, and resultantly improves device performance and reliability.

Grid-UMOSFET with electric field shielding of gate oxide

The present disclosure relates to transmission circuitry of a wireless communication device. The transmission circuitry includes power amplifier circuitry, an output matching network, and impedance control circuitry. The power amplifier circuitry amplifies a radio frequency (RF) input signal to provide an amplified RF output signal, which is passed through the output matching network and transmitted via one or more antennas. As the center frequency of the RF input signal and conditions of operating parameters change, the impedance control circuitry adjusts the values of one or more variable impedance elements of the output matching network in a desired fashion. The values of the variable impedance elements are adjusted such that the output matching network concurrently and dynamically presents the desired load impedances at the center frequency and at one or more harmonics of the RF input signal to achieve a given performance specification.

Matching network for transmission circuitry

A varactor diode includes a contact layer having a first conductivity type, a voltage blocking layer having the first conductivity and a first net doping concentration on the contact layer, a blocking junction on the voltage blocking layer, and a plurality of discrete doped regions in the voltage blocking layer and spaced apart from the carrier injection junction. The plurality of discrete doped regions have the first conductivity type and a second net doping concentration that is higher than the first net doping concentration, and the plurality of discrete doped regions are configured to modulate the capacitance of the varactor diode as a depletion region of the varactor diode expands in response to a reverse bias voltage applied to the blocking junction. Related methods of forming a varactor diode are also disclosed.

Varactor diode with doped voltage blocking layer

A dimpled substrate and method of making including a substrate of high thermal conductivity having a first main surface and a second main surface opposite the first main surface. Active epitaxial layers are formed on the first main surface of the substrate. Dimples are formed as extending from the second main surface into the substrate toward the first main surface. An electrical contact of low resistance material is disposed on the second main surface and within the dimples. A back contact of low resistance and low loss is thus provided while maintaining the substrate as an effective heat sink.

Silicon carbide dimpled substrate

A short gate high power metal oxide semiconductor field effect transistor formed in a trench includes a short gate having gate length defined by spacers within the trench. The transistor further includes a buried region that extends beneath the trench and beyond a corner of the trench, that effectively shields the gate from high drain voltage, to prevent short channel effects and resultantly improve device performance and reliability.

Short gate high power MOSFET and method of manufacture

A self-aligned, silicon carbide power metal oxide semiconductor field effect transistor includes a trench formed in a first layer, with a base region and then a source region epitaxially regrown within the trench. A window is formed through the source region and into the base region within a middle area of the trench. A source contact is formed within the window in contact with a base and source regions. The gate oxide layer is formed on the source and base regions at a peripheral area of the trench and on a surface of the first layer. A gate electrode is formed on the gate oxide layer above the base region at the peripheral area of the trench, and a drain electrode is formed over a second surface of the first layer.

Method of manufacturing silicon carbide self-aligned epitaxial MOSFET for high powered device applications

A unipolar semiconductor device having a drift layer () doped according to a first conductivity type forming a conducting path and regions () doped according to a second conductivity type and arranged next to the drift layer, has the drift layer and the regions of a semiconductor material having an ionization energy Ei of dopants of the second conductivity type therein exceeding 0.5 eV and/or a solubility of the dopants of the second conductivity type therein being less than 10cm.

Semiconductor device

A lateral field effect transistor for high switching frequencies having a source region layer () and a drain region layer () laterally spaced and of highly doped first conductivity type, a first-conductivity-type channel layer () of lower doping concentration extending laterally and interconnecting the source region layer () and the drain region layer (). The transistor has a gate electrode () arranged to control the properties of the channel layer (), and a second-conductivity-type base layer () arranged under the channel layer () at least partially overlapping the gate electrode () and at a lateral distance to the drain region layer (), the highly doped second-conductivity-type base layer () being shorted to the source region layer (). The transistor also has at least one of the following: a) a spacer layer () having semiconductor material adjacent to the channel layer () and located between the channel layer () and gate electrode (), at least in the vicinity of the gate electrode (), and/or b) a spacer layer () having semiconductor material adjacent to the channel layer () and located between the channel layer () and the second-conductivity-type base layer ().

Lateral field effect transistor and its fabrication comprising a spacer layer above and below the channel layer

A semiconductor device comprises a first layer () of a wide band gap semiconductor material doped according to a first conductivity type and a second layer () on top thereof designed to form a junction blocking current in the reverse biased state of the device at the interface to said first layer. The device comprises extension means for extending a termination of the junction laterally with respect to the lateral border () of the second layer. This extension means comprises a plurality of rings (-) in juxtaposition laterally surrounding said junction () and being arranged as seen in the lateral direction away from said junction alternatively a ring (-) of a semiconductor material of a second conductivity type opposite to that of said first layer and a ring (-) of a semi-insulating material.

Semiconductor device comprising a junction having a plurality of rings

A high electron mobility device and method of making is provided whereby a two-dimensional electron gas is formed at a hetero-junction or hetero-interface between different polytypes of a semiconductor material. The different crystal forms or polytypes of the semiconductor material having different electronic bandgaps are used to provide the bandgap necessary to form the two-dimensional electron gas.

Polytype hetero-interface high electron mobility device and method of making

A semiconductor device of unipolar type has Schottky-contacts () laterally separated by regions in the form of additional layers (&#x2033;) of semiconductor material on top of a drift layer (). Said additional layers being doped according to a conductivity type being opposite to the one of the drift layer. At least one (&#x2033;) of the additional layers has a substantially larger lateral extension and thereby larger area of the interface to the drift layer than adjacent such layers () for facilitating the building-up of a sufficient voltage between that layer and the drift layer for injecting minority charge carriers into the drift layer upon surge for surge protection.

Method for producing a field effect transistor having a source region (), a drain region and a channel layer () interconnecting the source and drain regions, and including the step of providing a sacrificial layer () on part of a semiconductor material () whose edge is used to define the edge of an implant, such as the source region (), in the semiconductor material (), where the edge () of the sacrificial layer () is subsequently used to define the edge of a gate ().

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Taby, Sweden

Christopher Harris