International Business Machines Corporation

Oracle International Corporation

Oracle America, Inc.

Sun Microsystems, Inc.

Motorola Corporation

Cadence Design Systems, Inc.

Christopher Hans Olson

Jeffrey S Brooks

Robert T Golla

Gregory Frederick Grohoski

Leonard D Rarick

Timothy A Elliott

Terence M Potter

Lawrence Spracklen

Robert Thaddeus Golla

Manish K Shah

Paul Joseph Jordan

Josephus Ebergen

Martin Stanley Schmookler

Paul J Jagodik

Lee Evan Eisen

Michael Putrino

Hesam Fathi Moghadam

Faraydon O Karim

Eugene Karichkin

John Stephen Muhich

David James Shippy

Peichun Peter Liu

Hoichi Cheong

Nils Gura

Bradley Gene Burgess

Michael Thomas Vaden

Robert Greg McDonald

Jama Ismail Barreh

Matthew B Smittle

Thomas Alan Ziaja

Thomas Alan Hoy

Albert John Loper

David Lawrence Rager

Thomas L Thomas, Jr

Carl D Dietz

Xiang Shan Li

Austin Lee

Tan V Chu

Tiberiu Carol Galambos

Jike Chong

Frank J Palermo

Dmitry Nadezhin

Dmitry Nadehzin

Josephus C Ebergen

Techniques are disclosed relating to an apparatus that includes a plurality of execution pipelines including first and second execution pipelines, a shared circuit that is shared by the first and second execution pipelines, and a decode circuit. The first and second execution pipelines are configured to concurrently perform operations for respective instructions. The decode circuit is configured to assign a first program thread to the first execution pipeline and a second program thread to the second execution pipeline. In response to determining that respective instructions from the first and second program threads that utilize the shared circuit are concurrently available for dispatch, the decode circuit is further configured to select between the first program thread and the second program thread.

Program thread selection between a plurality of execution pipelines

Control circuitry coupled to a multiply unit which includes a plurality of stage, each of which may be configured to perform a corresponding arithmetic function, may be configured to retrieve a given entry from a lookup table dependent upon a first portion of a binary representation of an input operand. An error value of an error function evaluated dependent upon a lookup value in a given entry of the plurality of entries is included in a predetermined error range. The control circuitry may be further configured to determine an initial approximation of a result of an iterative arithmetic operation using the first entry and initiate the iterative arithmetic operation using the initial approximation and the input operand.

Methods for constructing lookup tables for division and square-root implementations

Embodiments of a processor are disclosed for performing arithmetic operations on a machine independent number format. The processor may include a floating point unit, and a number unit. The number format may include a sign/exponent block, a length block, and multiple mantissa digits. The number unit may be configured to perform an operation on two operands by converting the digit format of each mantissa digit of each operand, to perform the operation using the converted mantissa digits, and then to convert each mantissa digit of the result of the operation back into the original digit format.

Floating point unit with support for variable length numbers

A multiplier unit may be configured to generate a final approximation of an iterative arithmetic operation performed on two operands. Circuitry coupled to the multiplier unit may perform a shift operation and a mask operation on the final approximation to generate shifted and un-shifted approximations, respectively. The circuitry may generate a first remainder using the un-shifted approximation and a sign value of a second remainder using the first remainder. Using the sign value of the second remainder, the circuitry may perform a rounding operation on the shifted approximation to generate a final answer.

Iterative division with reduced latency

A system that for storing program counter values is disclosed. The system may include a program counter, a first memory including a plurality of sectors, a first circuit configured to retrieve a program instruction from a location in memory dependent upon a value of the program counter, send the value of the program counter to an array for storage and determination a predicted outcome of the program instruction in response to a determination that execution of the program instruction changes a program flow. The second circuit may be configured to retrieve the value of the program counter from a given entry in a particular sector of the array, and determine an actual outcome of the program instruction dependent upon the retrieved value of the program counter.

Processing instruction control transfer instructions

Embodiments of a processor are disclosed for performing arithmetic operations on variable-length and fixed-length machine independent numbers. The processor may include a floating point unit, and a logic circuit. The number unit may be configured to receive an operation, and first and second operands. Each of the first and second operands may include a sign byte, and multiple mantissa bytes, and may be processed in response to a determination that the operands are fixed-length numbers. The logic circuit may be further configured to perform the received operation on the processed first and second operands.

Processing fixed and variable length numbers

A multiplier unit that may be configured to concurrently perform multiple division and square operations is disclosed. The multiplier unit may include multiple stages. Each stage may be configured to perform a corresponding arithmetic operation. Control circuitry coupled to the multiplier unit may be configured to schedule in a given cycle of the plurality of cycles, a respective tasks of a plurality of tasks included in a first operation for execution on a respective stage of the multiple stages. The control circuitry may be further configured to schedule execution of each tasks of a second plurality of tasks included in a second operation during a respective cycle on an unused stage of the multiple stages.

Scheduling multiple operations in a divider unit

A mechanism for handling unfused multiply-add accrued exception bits includes a processor including a floating point unit, a storage, and exception logic. The floating-point unit may be configured to execute an unfused multiply-accumulate instruction defined with the instruction set architecture (ISA). The unfused multiply-accumulate instruction may include a multiply sub-operation and an accumulate sub-operation. The storage may be configured to maintain floating-point exception state information. The exception logic may be configured to capture the floating-point exception state after completion of the multiply sub-operation and prior to completion of the accumulate sub-operation, for example, and to update the storage to reflect the floating-point exception state.

Mechanism for handling unfused multiply-accumulate accrued exception bits in a processor

A processor including instruction support for implementing the Camellia block cipher algorithm may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit that may receive instructions for execution. The instructions include one or more Camellia instructions defined within the ISA. In addition, the Camellia instructions may be executable by the cryptographic unit to implement portions of a Camellia cipher that is compliant with Internet Engineering Task Force (IETF) Request For Comments (RFC) 3713. In response to receiving a Camellia F( )-operation instruction defined within the ISA, the cryptographic unit may perform an F( ) operation, as defined by the Camellia cipher, upon a data input operand and a subkey operand, in which the data input operand and subkey operand may be specified by the Camellia F( )-operation instruction.

Apparatus and method for implementing instruction support for the camellia cipher algorithm

Systems and methods for providing single cycle movement of data between a floating-point register file (FRF) and a general purpose or integer register file (IRF) of a microprocessor system are provided. The system may include an integer execution unit operative to execute instructions with single cycle latency, a floating-point execution unit, a working register file (WRF), an FRF, and an IRF. To achieve the single cycle movement functionality, the integer execution unit may physically own the WRF, IRF, and FRF, and may monitor and control any dependencies between them. Thus, since the integer execution unit has direct read access to both the IRF and the FRF, data may be moved between the two register files using the single cycle operation of the integer execution unit, without the need to store and load the data from memory.

Single cycle data movement between general purpose and floating-point registers

Techniques are disclosed relating to integrated circuits that include hardware support for divide and/or square root operations. In one embodiment, an integrated circuit is disclosed that includes a division unit that, in turn, includes a normalization circuit and a plurality of divide engines. The normalization circuit is configured to normalize a set of operands. Each divide engine is configured to operate on a respective normalized set of operands received from the normalization circuit. In some embodiments, the integrated circuit includes a scheduler unit configured to select instructions for issuance to a plurality of execution units including the division unit. The scheduler unit is further configured to maintain a counter indicative of a number of instructions currently being operated on by the division unit, and to determine, based on the counter whether to schedule subsequent instructions for issuance to the division unit.

Division unit with normalization circuit and plural divide engines for receiving instructions when divide engine availability is indicated

Implementing an unfused multiply-add instruction within a fused multiply-add pipeline. The system may include an aligner having an input for receiving an addition term, a multiplier tree having two inputs for receiving a first value and a second value for multiplication, and a first carry save adder (CSA), wherein the first CSA may receive partial products from the multiplier tree and an aligned addition term from the aligner. The system may include a fused/unfused multiply add (FUMA) block which may receive the first partial product, the second partial product, and the aligned addition term, wherein the first partial product and the second partial product are not truncated. The FUMA block may perform an unfused multiply add operation or a fused multiply add operation using the first partial product, the second partial product, and the aligned addition term, e.g., depending on an opcode or mode bit.

Processor pipeline which implements fused and unfused multiply-add instructions

A pipelined circuit for performing a divide operation on small operand sizes. The circuit includes a plurality of stages connected together in a series to perform a subtractive divide algorithm based on iterative subtractions and shifts. Each stage computes two quotient bits and outputs a partial remainder value to the next stage in the series. The first and last stages utilize a radix-4 serial architecture with edge modifications to increase efficiency. The intermediate stages utilize a radix-4 parallel architecture. The divide architecture is pipelined such that input operands can be applied to the divider on each clock cycle.

Pipelined divide circuit for small operand sizes

Growing community of inventors

Austin, TX, United States of America

Christopher Hans Olson