Xilinx, Inc.

Christopher H Dick

Michael Wu

Raghavendar Mysore Rao

Frederic Joel Harris

Hongzhi Zhao

Richard Lewis Walke

Joseph R Cavallaro

Hemang Parekh

Nihat E Tunali

Kiarash Amiri

Christoph Emanuel Studer

Xiaohan Chen

Ralph D Wittig

Philip Bryn James-Roxby

Juan J Noguera Serra

Baris Ozgul

Kornelis Antonius Vissers

Jan Langer

Fredric Joel Harris

Jorn W Janneck

Hai-Jo Tarn

Goran H K Bilski

Bei Yin

Albert T Gural

Roger Brent Milne

Jonathan B Ballagh

Nabeel Shirazi

Jeffrey Stroomer

Ashish Sirasao

Raied N Mazahreh

Ashutosh Sabharwal

Bing Tian

Goran Hk Bilski

Peter McColgan

Vincent C Barnes

Benjamin J Egg

William A Wilkie

Satyaprakash Pareek

Yao Fu

Stephen Summerfield

Melissa Duarte

Anup Hosangadi

Nikolaus H Hammler

Aida Vosoughi

Frederick J Harris

Navid Laskharian

Oscar Fernando C Fernandez

Sambhav R Jain

Charles Jeon

Hemang M Parekh

Raghavendar M Rao

Disclosed approaches for convolving input feature maps in a neural network include a circuit arrangement circuit that includes memory circuitry and convolution circuitry. The memory circuitry is configured to store K NxN first filters, and C 1x1 second filters, wherein N &#x2265; 1, and 1 < K < C. The convolution circuitry is coupled to the memory circuitry and configured to convolve a three-dimensional input feature map with the K NxN first filters into an intermediate volume having a depth of K, and convolve the intermediate volume with the C 1x1 second filters into an output feature map having a depth of C.

Convolution circuitry

Systems and methods for training a neural network model includes providing a quantization function including a quantization log threshold parameter associated with a log value of a quantization threshold. A quantization training to a neural network model is performed to generate quantized neural network parameters. The quantization training includes: generating first values with a first precision for the neural network parameters; performing a first optimization process to generate an updated quantization log threshold parameter; and generating quantized values with a second precision lower than the first precision for the neural network parameters by applying the quantization function with the updated quantization log threshold parameter to the first values. The neural network model with the quantized values for the neural network parameters is provided for performing a task.

System and method for implementing neural networks in integrated circuits

Method and system relating generally to convolution is disclosed. In such a method, an image patch is selected from input data for a first channel of a plurality of input channels of an input layer. The selected image patch is transformed to obtain a transformed image patch. The transformed image patch is stored. Stored is a plurality of predetermined transformed filter kernels. A stored transformed filter kernel of the plurality of stored predetermined transformed filter kernels is element-wise multiplied by multipliers with the stored transformed image patch for a second channel of the plurality of input channels different from the first channel to obtain a product. The product is inverse transformed to obtain a filtered patch for the image patch.

Method and system for convolution

A device may include a plurality of data processing engines. Each of the data processing engines may include a memory pool having a plurality of memory banks, a plurality of cores each coupled to the memory pool and configured to access the plurality of memory banks, a memory mapped switch coupled to the memory pool and a memory mapped switch of at least one neighboring data processing engine, and a stream switch coupled to each of the plurality of cores and to a stream switch of the at least one neighboring data processing engine.

Data processing engine arrangement in a device

Lossy tensor compression and decompression circuits compress and decompress tensor elements based on the values of neighboring tensor elements. The lossy compression circuit scales each decompressed tensor element of a tile by a scaling factor that is based on the maximum value that can be represented by the number of bits used to represent a compressed tensor element, and the greatest value and least value of the tensor elements of the tile. The lossy decompression circuit performs the inverse of the lossy compression. The compression circuit and decompression circuit have parallel multiplier circuits and parallel adder circuits to perform the lossy compression and lossy decompression, respectively.

Tensor compression

A decoder circuit includes a low-density parity-check (LDPC) repository, an LDPC code configurator, and LDPC decoding circuitry. The LDPC repository stores parity-check information associated with one or more LDPC codes. The LDPC code configurator may receive a first LDPC configuration describing a parity-check matrix for a first LDPC code and may update the parity-check information in the LDPC repository to reflect the parity-check matrix for the first LDPC code. The LDPC decoding circuitry may receive a first codeword encoded in accordance with the LDPC code. More specifically, the LDPC decoding circuitry may be configured to read the parity-check information associated with the first LDPC code from the LDPC repository and iteratively decode the first codeword using the parity-check information associated with the first LDPC code.

User-programmable LDPC decoder

Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include a memory module (with memory banks for storing data) and an interconnect which provides connectivity between the engines. To transmit processed data, a data processing engine identifies a destination processing engine in the array. Once identified, the data processing engine can transmit the processed data using a reserved point-to-point communication path in the interconnect that couples the source and destination data processing engines.

Streaming interconnect architecture for data processing engine array

A digital predistortion (DPD) system includes an input configured to receive a DPD input signal. In some embodiments, a non-linear datapath is coupled to the input, where the non-linear datapath includes a plurality of parallel datapath elements each coupled to the input. By way of example, each of the plurality of parallel datapath elements is configured to add a different inverse non-linear component to the DPD input signal corresponding to a non-linear component of an amplifier. In various examples, a first combiner combines an output of each of the plurality of datapath elements to generate a first predistortion signal. In some embodiments, the DPD system further includes a linear datapath coupled to the input in parallel with the non-linear datapath to generate a second predistortion signal. In addition, a second combiner combines the first predistortion signal and the second predistortion signal to generate a DPD output signal.

Method of and circuit for predistortion for a cable TV amplifier

A device may include a plurality of data processing engines. Each data processing engine may include a core and a memory module. Each core may be configured to access the memory module in the same data processing engine and a memory module within at least one other data processing engine of the plurality of data processing engines.

Device with data processing engine array

Circuits and method for multiplying floating point operands. An exponent adder circuit sums a first exponent and a second exponent and generates an output exponent. A mantissa multiplier circuit multiplies a first mantissa and a second mantissa and generates an output mantissa. A first conversion circuit converts the output exponent and output mantissa into a fixed point number. An accumulator circuit sums contents of an accumulation register and the fixed point number into an accumulated value and stores the accumulated value in the accumulation register.

Multiply and accumulate circuit

A digital predistortion (DPD) system includes an input configured to receive a DPD input signal. In some examples, a non-linear datapath is coupled to the input, where the non-linear datapath is configured to add a non-linear mirror image component to the DPD input signal to provide a non-linear signal that is used to generate a first predistortion signal. In some embodiments, a linear datapath is coupled to the input in parallel with the non-linear datapath to generate a second predistortion signal. A first combiner is configured to combine the first predistortion signal and the second predistortion signal to generate a DPD output signal.

A modem includes an outer transceiver including a soft decision forward error correction (SD-FEC) circuit, wherein the SD-FEC circuit is hardwired and programmable to perform at least one of encoding or decoding data using a code type selected from a plurality of different code types, and an inner transceiver coupled to the SD-FEC circuit, wherein the inner transceiver is implemented in programmable circuitry.

Software defined modem

Described examples provide for digital communication circuits and systems that implement digital pre-distortion (DPD). In an example, a circuit includes a baseband DPD circuit, up-conversion circuitry, and feedback circuitry. The baseband DPD circuit comprises a baseband signal path and pre-distortion path. The pre-distortion path is configured to generate a pre-distortion signal based on the baseband signal. The baseband DPD circuit includes a first adder configured to add the baseband signal from the baseband signal path and the pre-distortion signal from the pre-distortion path to generate a pre-distorted baseband signal. The up-conversion circuitry is configured to convert the pre-distorted baseband signal to a radio frequency signal. The up-conversion circuitry is configured to be coupled to an input of a cable television (CATV) amplifier. The feedback circuitry comprises a DPD engine configured to determine a configuration of the pre-distortion path based on an output signal on the output of the CATV amplifier.

Digital communications circuits and systems

A decoder circuit includes an input configured to receive an encoded message generated based on a QC-LDPC code. A first layer process unit is configured to process a first layer of a parity check matrix to generate a plurality of log-likelihood ratio (LLR) values corresponding to a plurality of variable nodes associated with the encoded message respectively. The first layer process unit includes a plurality of row process units configured to process a first plurality of rows of the first layer in parallel to generate a plurality of row update values. A layer update unit is configured to generate a first LLR value for a first variable node using first and second row update values for the first variable node. An output is configured to provide a decoded message generated based the plurality of LLR values.

Systems and methods for decoding quasi-cyclic (QC) low-density parity-check (LDPC) codes

A crest factor reduction (CFR) system includes a digital tilt filter coupled to an input of the CFR system. In some embodiments, the digital tilt filter is configured to receive a system input signal and generate a digital tilt filter output signal at a digital tilt filter output. In some examples, the CFR system further includes a CFR module coupled to the digital tilt filter output, where the CFR module is configured receive the digital tilt filter output signal and perform a CFR process to the digital tilt filter output signal to generate a CFR module output signal at a CFR module output. In addition, the CFR system may include a digital tilt equalizer coupled to the CFR module output, where the digital tilt equalizer is configured to receive the CFR module output signal and generate a system output signal.

Method of and circuit for crest factor reduction for a cable TV amplifier

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San Jose, CA, United States of America

Christopher H Dick