Hewlett-Packard Development Company, L.p.

Christopher Greer

Richard W Adkisson

Gary Belgrave Gostin

Michael Alex Schroeder

Huai-Ter Victor Chong

A method of operating a central cache controller ('CCC') in a first cell of a multiprocessor system comprising multiple cells each including globally shared memory ('GSM'), wherein the first cell is disposed in a first partition and the CCC is connected to a plurality of CPUs of the first cell. In one embodiment, the method comprises, responsive to a new transaction request from one of the CPUs, logging the transaction in a transaction table; determining whether an identity marker in a timeout map corresponding to a cell to which the transaction was issued is set; and, responsive to the corresponding identity marker in the timeout map being set, immediately returning a special error to the one of the CPUs that requested the transaction.

Timeout acceleration for globally shared memory transaction tracking table

Transferring cache line ownership between processors in a shared memory multi-processor computer system. A request for ownership of a cache line is sent from a requesting processor to a memory unit. The memory unit receives the request and determines which one of a plurality of processors other than the requesting processor has ownership of the requested cache line. The memory sends an ownership recall to that processor. In response to the ownership recall, the other processor sends the requested cache line to the requesting processor, which may send a response to the memory unit to confirm receipt of the requested cache line. The other processor may optionally send a response to the memory unit to confirm that the other processor has sent the requested cache line to the requesting processor. A copy of the data for the requested cache line may, under some circumstances, also be sent to the memory unit by the other processor as part of the response.

Cache line ownership transfer in multi-processor computer systems

Systems and methods for increasing transaction entries in a hardware queue of the type having a fixed number of storage elements. One of a plurality of transaction entries in one of the storage elements is accessed through at least one pointer having one or more first bits that identify the one element and one or more second bits that identify the one transaction entry within the one element. Information that is part of the one transaction entry is modified when the one transaction entry is accessed from the one storage element.

Systems and methods for increasing transaction entries in a hardware queue

Systems and methods generate transaction identifiers. A plurality of available transaction identifiers are generated for use in identifying future transactions from a first bus. A new transaction identifier is generated upon receipt of each received transaction from the first bus. One of the available transaction identifiers is assigned to each received transaction prior to generation of the new transaction identifier so that the received transaction communicated on a second bus is identified by the one transaction identifier.

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Allen, TX, United States of America

Christopher Greer