Advanced Micro Devices Corporation

Christopher Gray

Michael T Wisor

Travis Wheatley

A method and system for testing a plurality of addressing modes in a microprocessor comprising executing a test instruction which is stored in memory, subsequently overwriting the test instruction in memory and then re-executing the test instruction. The test instruction is stored at a memory location which is within a code segment. A data segment is defined to overlap with the code segment and a portion of the test instruction is overwritten by storing data within the overlapping data segment. The overwritten portion of the test instruction identifies the addressing mode of the test instruction and the stored data represents the next addressing mode to be tested. In an x86 architecture, the overwritten portion of the test instruction may comprise a MODR/M byte and an SIB byte, each of which may take on values from 00 to ff (hexadecimal). The addressing modes of the microprocessor may therefore be tested by sequentially incrementing the MODR/M and SIB bytes and executing the test instruction.

Self modifying code to test all possible addressing modes

A method and system for verifying the accuracy of trace data generated by execution of a program on a computer under test, one embodiment of the method comprising scanning the trace data to locate bitmap data corresponding to series of consecutive conditional branches and comparing the number of bits representative of these branches to the number of consecutive conditional branches in the instruction sequence. The trace data includes address entries and bitmap entries. The trace data is scanned in reverse chronological order beginning with the most recent entry to locate an address entry preceding one or more bitmaps which represent a most recent series of conditional branches. Beginning with the instruction at the address contained in the address entry, the program instructions are scanned in program order until a conditional branch is encountered. The branch is counted and the trace data is examined to determine whether the branch was taken and scanning is resumed. The scanning and counting of the conditional branches continues until an instruction which generates a non-bitmap entry is encountered. The number of conditional branches is then compared to the number of bits representative of branches to verify that they are equal. In some embodiments, the target addresses of the branch instructions are also checked to verify that they correspond to the target addresses of the corresponding BTHB entries. Preceding bitmap entries are each checked in this manner until all of the trace data has been verified.

Method for verifying branch trace history buffer information

A method for determining the default operating mode of a code segment by determining whether an instruction modifies bits in both the upper-order and lower-order halves of a register. A register is set to a known value and an instruction which operates on the register is subsequently executed. After execution of the instruction, it is determined whether the high-order bits of the register have been modified by the instruction. If the instruction modifies the high-order bits of the register, a first default mode is indicated and, if the instruction does not modify the high-order bits of the register, a second default mode is indicated.

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Austin, TX, United States of America

Christopher Gray