Infineon Technologies Richmond, LP

Infineon Technologies Ag

Christopher Gould

William Roberts

Gerhard Kunkel

Shoaib Hasan Zaidi

Ulrich Mantz

Xiaoming Yin

Nicholas Louka

Abeer Singhal

Targets or test structures used for measurements in semiconductor devices having long lines exceeding design rule limitations are divided into segments. In one embodiment, the segments have periodicity in a direction parallel to the length of the lines. In another embodiment, the segments of test structures in adjacent lines do not have periodicity in a direction parallel to the length of the lines. The lack of periodicity is achieved by staggering segments of substantially equal lengths in adjacent lines, or by dividing the lines into segments having unequal lengths. The test structures may be formed in scribe line regions or die regions of a semiconductor wafer.

Targets for measurements in semiconductor devices

A method and apparatus according to the present invention define optimal conditions for a scanning electron microscope (SEM), preferably a critical dimension scanning electron microscope (CDSEM). The present invention provides an image quality monitor that utilizes image processing and optimization to maintain image quality at a desired level. Images from a stage sample are automatically collected, while microscope operational parameters are determined based on image processing to enable continuous monitoring of microscope operation. The technique may be performed manually or automatically and generates set points for beam conditioning elements to produce or maintain ideal beam conditions to enhance image quality. The present invention generates data indicating optimized values for each beam alignment parameter. The optimized values are applied to the internal microscope values to optimize the beam. The results may be provided to the technician, a data storage system or directly to the microscope control mechanisms.

Method and apparatus for automated beam optimization in a scanning electron microscope

A method of controlling lithographic overlay offsets in the manufacture of semiconductor devices from wafers, comprising the steps of forming a lithographic pattern on a wafer layer with a lithographic tool, processing the wafer after the pattern is formed to enable fabrication of a semiconductor device, predicting overlay offset corrections based on one or more factors involved in the processing of the wafer, and utilizing the predicted overlay offset corrections to positionally control the lithographic tool.

Lithography method and system with correction of overlay offset errors caused by wafer processing

The disclosed system and method relates to the prediction of processing tool control parameters, i.e. controller state, for a particular processing tool, which has little or no utilization history, i.e. is data starved or has not gone through the learning curve, for a given process, or has undergone an event for which the current controller state has been reset or is otherwise now sub-optimal. The prediction is based on the processing tool control parameters of a substantially similar processing tool, being used in a substantially similar fashion to the given situation, which has significant utilization history. The processing tool having significant utilization history may be the same processing tool as the processing tool with little or no processing history where a manufacturing event disrupts the operations thereof. In this case, the pre-event control parameters and utilization history may be used, according to the disclosed embodiments, to predict the post-event controller state. Effectively, the disclosed embodiments provide for the processing tool with little or no utilization history to inherit the controller state, i.e. the evolved control parameters, of the processing tool with significant utilization history. Thereby, the processing tool with little or no utilization history is spared having to go through the learning curve, and the associated costs in delay and resources, to arrive at a particular controller state, i.e. the processing tool does not have to go through the iterative process-evaluate-adapt procedure to refine its control parameters to achieve results within the desired specifications.

System and method to predict the state of a process controller in a semiconductor manufacturing facility

In an overlay measurement mark comprising an inner box and an outer box located at a predetermined area on a mask through which patterns are formed on a semiconductor device, the improvement of an overlay mark that extends the overlay measurement range comprising: in-focused marks means printed at an optimal or ideal focal plane level from an illumination source, and de-focused marks means located at a different focus level from the optimal focal plane to provide image placement shift of the de-focused marks larger than that of the in-focused marks means to enable measurement of the shift of de-focused marks that are not attributable to a mechanical alignment error to be determined with greater accuracy.

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Quinton, VA, United States of America

Christopher Gould