Micron Technology Incorporated

Lodestar Licensing Group LLC

Christopher Gordon Wieduwilt

James S Rehmeyer

Seth A Eichmeyer

Jason M Johnson

Yoshinori Fujiwara

Alan John Wilson

Kevin Gustav Werhane

Dennis G Montierth

Daniel S Miller

Matthew D Jenkinson

Dean D Gans

Fatma Arzum Simsek-Ege

George B Raad

Christian N Mohr

Gregg D Wolff

C Omar Benitez

Vivek Kotti

Lawrence D Smith

Kenji Yoshida

Matthew Alan Prather

Jiyun Li

Sangmin Hwang

Kyuseok Lee

Boon Hor Lam

Minoru Someya

Shawn M Hilde

Greg S Hendrix

Toshihiko Miyashita

Eric J Rich-Plotkin

John P Behrend

Eric J Schultz

A microelectronic device comprises a periphery circuitry region, bank regions, a control circuitry structure, and a memory array structure. The periphery circuitry region comprises a central sub-region, and two arm sub-regions extending from the central sub-region from the central sub-region in a first horizontal direction. Each of the two arm sub-regions has a different length than the central sub-region in a second horizontal direction orthogonal to the first horizontal direction. The bank regions are horizontally outward of the periphery circuitry region. The control circuitry structure comprises relatively more speed-critical circuitry within a horizontal area of the periphery circuitry region, and relatively less speed-critical circuitry within horizontal areas of the bank regions. The memory array structure vertically underlies the control circuitry structure and comprises arrays of memory cells within the horizontal areas of the bank regions. Additional microelectronic devices and memory devices are also described.

Microelectronic devices and memory devices

Systems are disclosed. A system may include a host device, a first memory device, and a second memory device. Each of the first memory device and the second memory device are configured to be refreshed substantially simultaneously responsive to a receipt of a refresh command from the host device. A count value of a refresh address counter of the first memory device is different than a count value of a refresh address counter of the second memory device. Associated methods are also described.

Staggering refresh address counters of a number of memory devices, and related methods, devices, and systems

Fuses can store different delay states to cause execution of a command to be staggered for different memory dies of a memory package. Fuse arrays can be included in the memory package and programmed to cause execution of a command to be delayed by different amounts for different dies. The fuse arrays can be fabricated and then programmed to cause different delays for different dies.

Fuse delay of a command in a memory package

An antifuse device, including a gate having a gate dielectric layer; a first doping region connected to a first end of the gate; a second doping region connected to a second end of the gate, the second end being opposite to the first end of the gate; a channel that is disposed under the gate and that connects the first doping region and the second doping region; and an interconnection jumper that electrically connects the first doping region and the second doping region.

Antifuse device having interconnect jumper

An improved memory module and methods for constructing the same are disclosed herein. The memory module includes a substrate having a first surface and a second surface opposite the first surface, each having a central portion, a first array area and a second array area. The first array area is cooler than the second array area during operation. The memory module also includes a power management integrated circuit attached to the central portion of the first surface. The memory module also includes a first semiconductor die attached to the substrate in the first array area. The first semiconductor die has a first performance rating of an operating parameter at high temperatures. The memory module also includes a second semiconductor die attached to the substrate in the second array area. The second semiconductor die has a second performance rating of an operating parameter better than the first performance rating at high temperatures.

Management of heat on a semiconductor device and methods for producing the same

Global column repair with local column decoder circuitry and related apparatuses, methods, and computing systems are disclosed. An apparatus includes global column repair circuitry including column address drivers corresponding to respective ones of column planes of a memory array. The column address drivers are configured to, if enabled, drive a received column address signal to local column decoder circuitry local to respective ones of the column planes. The global column repair circuitry also includes match circuitry and data storage elements configured to store defective column addresses corresponding to defective column planes. The match circuitry is configured to compare a received column address indicated by the received column address signal to the defective column addresses and disable a column address driver corresponding to a defective column plane responsive to a determination that the received column address matches a defective column address associated with the defective column plane.

Global column repair with local column decoder circuitry, and related apparatuses, methods, and computing systems

A memory device includes a plurality of fuse banks for a memory region. Each fuse bank stores bit information that relates to at least one of a default address for the plurality of fuse banks or an address of a memory cell that is defective. A default address protection circuit is configured to provide a default address status signal indicating whether a fuse bank in the plurality of fuse banks is storing bit information that corresponds to both the default address and an address of a memory cell that is defective. The memory device include a no_match circuit that overrides a repair of the external memory address if the external address matches the default address and if the default address status signal indicates that no fuse bank is storing bit information that corresponds to both the default address and an address of a memory cell that is defective.

Unused redundant enable disturb protection circuit

Apparatuses and methods for controlling sense amplifier operation are described. An example method includes providing a control signal having a first high logic level voltage to activate isolation switches of a sense amplifier. The control signal transitions from the first high logic level voltage to an inactive voltage to deactivate the isolation switches of the sense amplifier before accessing a memory cell. The control signal is provided having the first high logic level voltage to activate the isolation switches of the sense amplifier after accessing the memory cell. The control signal is increased from the first high logic level voltage to a second high logic level voltage.

Apparatuses and methods for controlling sense amplifier operation

Signaling indicative of a command to initialize a plurality of memory dies of a memory device can be received by the memory device. Initialization of a memory die of the memory device can be delayed, at the memory die and based at least in part on fuse states of an array of fuses of the memory die, by an amount of time relative to receipt of the signaling by the memory device. Delaying initialization of memory dies of the memory device in a staggered or asynchronous manner can evenly distribute power consumption of the memory dies so that the likelihood of an associated power spike is reduced or eliminated.

Delay of initialization at memory die

Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. One or more error correction code (ECC) may be used to determine if the bits of information contain any errors. To mitigate the effects of failures of adjacent memory cells, the information may be divided into a first group and a second group, where each group contains information from memory cells which are non-adjacent to other memory cells of that group. Each group of information may include data bits and parity bits used to correct those data bits. For example, as part of a read operation, a first ECC circuit may receive information from even numbered memory cells, while a second ECC circuit may receive information from odd numbered memory cells.

Apparatuses, systems, and methods for error correction

Apparatuses and methods can be related to placing memory in a computing system. The memory modules can be placed in memory slots to couple the memory modules to the computing system. The memory modules and/or the memory slots can have thermal qualities which can be utilized to determine which of the memory modules are placed on which of the memory slots.

Memory placement in a computing system

A timing of an execution of a command in a memory device can be affected delay elements. The delay elements of a unit of delay elements can cause variable delays of the command paths. The delay elements can be activated based on settings stored in a fuse array of a memory device. The delay elements can be used to change a timing of current draw of the memory devices.

Delay elements for command timing in a memory device

A memory device includes a memory cell array and a set of fuse banks including a common fuse bank storing common bit information corresponding to a plurality of defective memory cells in the memory cell array. The memory device including a plurality of match sub-circuits corresponding to respective defective memory cells of the plurality of defective memory cells. Each match sub-circuit can be configured to provide a determination of whether a memory cell address of a memory cell of the memory cell array matches an address of the respective defective memory cell. The plurality of match sub-circuit can include a shared common bit-processing circuit that is configured to receive common bit-by-bit results of a comparison between a portion of the memory cell address and the common bit information. The common bit-processing circuit can determine whether the common bit information matches the portion of the memory cell address.

Shared components in fuse match logic

Methods, systems, and devices for indicating a blocked repair operation are described. A first indication of whether an address of a memory device is valid may be stored. After the first indication is stored, a command for accessing the address may be processed. Based on processing the command, a second indication of whether the address is valid may be obtained, and a determination of whether to perform or prevent a repair operation for repairing the address may be made based on the first indication and the second indication. A third indication of whether the repair operation was performed or prevented may be stored.

Growing community of inventors

Boise, ID, United States of America

Christopher Gordon Wieduwilt