Hewlett-packard Company

National Semiconductor Corporation

Cyrix Corporation

Christopher G Wilcox

Russ William Herrell

Willard S Briggs

Brian Dennis Falardeau

Forrest E Norrod

Curtis R McAllister

Joseph F Baldwin

Xiaoli Y Mendyke

Sameer Y Nanavati

Dong Y Kuo

Joe Baldwin

A processing system having a CPU core and a cache transfers data between a first block of memory and a second block of memory that is preferably partitioned out of the cache as a non-cacheable scratchpad area and performs address calculations with protection and privilege checks without polluting the cache. Responsive to executing a predetermined instruction, the CPU core signals the cache to prevent caching data during transfer from system to scratchpad memory thereby reducing the number of bus turnarounds while maintaining byte granularity addressability.

Data transfer with highly granular cacheability control between memory and a scratchpad area

A processing system includes a graphics subsystem that directly renders raster data to system memory and moves bitmaps between locations within system memory with the graphics subsystem providing the data and a processor providing the virtual-to-physical addresses with privilege and protection check mechanisms.

Data transfer from a graphics subsystem to system memory

An enhanced system management mode (SMM) includes nesting of SMI (system management interrupt) routines for handling SMI events. Enhanced SMM is implemented in an computer system to support a Virtual System Architecture (VSA) in which peripheral hardware, such as for graphics and/or audio functions, is virtualized (simulated by SMI routines). Reentrant VSA/SMM software (handler) includes VSA/SMI routines invoked either by (a) SMI interrupts, such as from non-virtualized peripheral hardware such as audio FIFO buffers, or (b) SMI traps, such as from accesses to memory mapped or I/O space allocated to a virtualized peripheral function. SMI nesting permits a currently active VSA/SMI routine to be preempted by another (higher priority) SMI event. The SMM memory region includes an SMI header segment and a VSA/SMM software segment--the SMI header segment is organized as a quasi-stack into which nested SMI headers are saved. The VSA/SMM software manages an SMHR register that points to the location for storing the SMI header for a currently active VSA/SMI routine if it is preempted by an SMI event. To improve performance, the entire SMM region is mapped into cacheable system memory. Features that support virtualization include: (a) SMI nesting, (b) SMI trapping for memory (as well as I/O) accesses, (c) caching both VSA/SMI headers and VSA/SMM software, and (d) configuring the SMM region for storing multiple SMI headers at programmable locations.

Enhanced system management mode with nesting

A system for implementing polygon edging of objects in a graphics display. In a first pass, the system renders the polygon fill with z-buffer comparison and replace enabled, however, for each pixel written to the display frame buffer and z-buffer, an edging plane bit for the pixel is set. A second pass renders the polygon edges with z-buffer comparison and z-buffer replace enabled and uses the edging plane bit as a virgin bit. A third pass re-renders the polygon fill, but only resets the edging plane bit for each pixel. The system may also use a virgin bit available in the z-buffer as the edging plane bit.

Method for displaying edging or decaling of an object in a graphics

The present invention relates to an intelligent direct memory access (DMA) controller which interprets user commands from a host system, establishes work buffers for each user process, and retrieves blocks of data from the work buffers at the user's is request, rather than at the request of the kernel software. This is accomplished by establishing work buffers for each user process which are locked into physical memory. The controlling user process will then fill one work buffer, acquire the device semaphore, start physical DMA on the locked buffer, and then start filling another buffer. Memory integrity is maintained by allowing the user to access the work buffers for DMA without knowing their physical location in memory, via work buffer pointers from work buffer pointer registers which correspond to each work buffer for each user process. These work buffer pointer registers are privileged and are updated by the host processor for each new controlling user process.

Growing community of inventors

Ft. Collins, CO, United States of America

Christopher G Wilcox