Apple Inc.

Network Appliance, Inc.

Christopher G Peak

Joseph Sokol, Jr

Martin Scheinberg

Jeffrey S Kimmel

Umesh Suresh Vaishampayan

Guy G Sotomayor

Daniel Heller

Sathya Bettadapura

A system and method are described for warming a processor from a low power state in anticipation of a time critical interrupt. For example, one embodiment of a method comprises: detecting that a time-critical interrupt will require processor resources at some point in the future; estimating a time at which the time-critical interrupt will be triggered; scheduling a timer interrupt to fire at a specified time prior to the estimated time that the time-critical interrupt will be triggered, the timer interrupt being scheduled with sufficient time to ensure that the processor is warmed to a level at which it is capable of handling the time-critical interrupt at the time that the time-critical interrupt is triggered; and responsively triggering the timer interrupt at the specified time prior to the time critical interrupt.

System and method for adjusting power usage to reduce interrupt latency

Embodiments of the present invention provide a system that maps an N-bit application to virtual memory. The N-bit application may be obtained by porting an M-bit application to an N-bit architecture where N is greater than M. During operation, the system receives a request to map an N-bit application to a computer's virtual memory. The system then maps the N-bit application to a section of virtual memory which begins at a memory address that is greater than or equal to 2. If the N-bit application accesses a memory address which is less than 2, the system can generate a trap, thereby facilitating the discovery of M-bit memory references in the N-bit application.

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One embodiment of the present invention provides a system that uses an M-bit operating system (OS) kernel to support N-bit user processes. During operation, the system receives an exception. Note that the exception can be any event that needs to be handled by executing OS kernel code. Specifically, the exception can be a hardware interrupt, a software interrupt, an asynchronous interrupt, a synchronous interrupt, a signal, a trap, or a system call. Next, the system handles the exception by first switching the processor to the M-bit mode, and then executing M-bit OS kernel code which is designed to handle the exception. Note that the processor may primarily be designed to operate in the N-bit mode; the M-bit mode may primarily be provided for backward compatibility reasons.

Processing exceptions from 64-bit application program executing in 64-bit processor with 32-bit OS kernel by switching to 32-bit processor mode

An analyzer that analyzes instructions and data to determine where the instructions and data might result in incorrect results when run on a multiprocessor system. The instructions and data are divided into plural domains based on the symbols used to refer to those instructions and data, and the multiprocessor system is configured to use at most one processor at a time to execute instructions and to access data from any one domain. The analyzer preferably includes a reference analyzer and a table generator. The reference analyzer determines which of the instructions and data involve references outside of their domains, and determines which of the references outside of their domains are multiprocessor unsafe references. The report generator generates a report of the multiprocessor unsafe references. Also, a checker that dynamically determines where instructions and data result in domain violations when run on a multiprocessor system. The checker includes an interface to a table of purportedly microprocessor safe references by the instructions and data outside of their domains. The table preferably includes the domains to which the references are supposed to refer. The checker also includes a reference tracker that tracks references made by the instructions and data, and a comparator that determines, when a reference in the table of purportedly microprocessor safe references is encountered during execution of the instructions and data, if the reference is actually to a domain to which that reference is supposed to refer.

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San Jose, CA, United States of America

Christopher G Peak