Spansion Llc.

Advanced Micro Devices Corporation

Globalfoundries Inc.

Christopher Foster

Yu Nan Sun

Hiroyuki Kinoshita

Christopher F Lyons

Cyrus E Tabery

Christopher H Raeder

Timothy Z Hossain

Greg Alan Goodwin

John R Behnke

Patrick Mark Clopton

Dan E Posey

Basab Banerjee

Minh Van Ngo

Unsoon Kim

Kashmir S Sahota

Kouros Ghandehari

Krishnashree Achuthan

Harpreet Kaur Sachar

Hirokazu Tokuno

Weidong Qian

David H Matsumoto

Clayton Fullwood

Clayton Fulwood

Systems and methods are described herein for detecting particles emitted by nuclear material. The systems comprise one or more semiconductor devices for detecting particles emitted from nuclear material. The semiconductor devices can comprise a charge storage element comprising several layers. A non-conductive charge storage layer enveloped on top and bottom by dielectric layers is mounted on a substrate. At least one top semiconductor layer can be placed on top of the top dielectric layer. A reactive material that reacts to particles, such as neutrons emitted from nuclear material, can be incorporated into the top semiconductor layer. When the reactive material reacts to a particle emitted from nuclear material, ions are generated that can alter the charge storage layer and enable detection of the particle.

Charge storage device for detecting alpha particles

System and method for detecting particles with a semiconductor device

A method includes forming a layer of silicon oxynitride (SiON), silicon rich nitride (SiRN) or silicon nitride (SiN) over a layer of semiconducting material. The method further includes forming a first layer of anti-reflective material over the layer of SiON, SiRN or SiNand forming a second layer of anti-reflective material over the first layer. The method also includes using the first layer, second layer and layer of SiON, SiRN or SiNas a mask when etching a pattern in the layer of semiconducting material.

Triple layer anti-reflective hard mask

A method is disclosed for the definition of the poly-1 layer in a semiconductor wafer. A non-critical mask is used to recess field oxides in the periphery prior to poly-1 deposition by an amount equal to the final poly-1 thickness. A complimentary non-critical mask is used to permit CMP of the core to expose the tops of core oxide mesas from the shallow isolation trenches.

Non-critical complementary masking method for poly-1 definition in flash memory device fabrication

A method for forming a semiconductor device that includes a line and space pattern with variable pitch and critical dimensions in a layer on a substrate. The substrate includes a first region (e.g., a core region) and a second region (e.g., a periphery region). A first sub-line and space pattern in the first region comprises a space of a dimension (A) less than achievable by lithographic processes alone. Further, a second sub-line and space pattern in the second region comprises at least one line including a second critical dimension (B) achievable by lithography. The method uses two critical masking steps to form a hard mask that includes in the core region a critical dimension (A) less than achievable at a resolution limit of lithography. Further, the method uses a single etch step to transfer the pattern of the hard mask to the layer.

Semiconductor device with core and periphery regions

METHOD OF FORMING CORE AND PERIPHERY GATES INCLUDING TWO CRITICAL MASKING STEPS TO FORM A HARD MASK IN A CORE REGION THAT INCLUDES A CRITICAL DIMENSION LESS THAN ACHIEVABLE AT A RESOLUTION LIMIT OF LITHOGRAPHY

Growing community of inventors

Austin, TX, United States of America

Christopher Foster