Altera Corporation

Applied Materials, Inc.

Brooks Automation Gmbh

Yield Engineering Systems, Inc.

Other

Cercom, Inc.

Altera Corporation San Jose Ca

Christopher F Lane

Srinivas T Reddy

Andy Louie Lee

Richard G Cliff

Bruce B Pedersen

Cameron R McClintock

David Edward Jefferson

Ketan H Zaveri

David Lewis

Vaughn Betz

Manuel M Mejia

Paul Leventis

Kerry S Veenstra

Vikram Santurkar

Kevin P Fairbairn

Brian D Johnson

Joseph Huang

David Wolk Mendel

Francis B Heile

Chris Wysocki

Alexander Marquardt

Chiakang Sung

Bonnie I Wang

Mario E Guzman

Kelly A Colborne

L Todd Cope

Craig S Lytle

Henry Kim

Ninh D Ngo

Giles V Powell

Rina Raman

Michael S Barnes

Sasson Roger Somekh

Ramanand Venkata

Terry Bluck

James G Schleicher

Dana How

Satish Sundar

Hyun Mo Yi

Fung Fung Lee

Steven Verhaverbeke

Jeffrey T Watt

David Wingto Cheung

Arifur Rahman

Shamouil Shamouilian

Michael Santiago Cox

Peter K Loewenhardt

Hari K Ponnekanti

Canfeng Lai

Jinyong Yuan

Srinivas Perisetty

John P Parks

M Ziaul Karim

Mark A Fodor

Wayne Yeung

Tim Michael Vanderhoek

J Kelly Truman

Michael Chan

Robert R Bielby

Thomas Yau-Tsun Wong

Robert Richard Noel Bielby

Robert B Majewski

David P Wanamaker

Sarathy Sribhashyam

Timothy Vanderhoek

Dan Maydan

Ashok K Sinha

Keith Duwel

Hui Liu

Tomoyuki Fujii

Howard E Grunes

Hideyoshi Tsuruta

Wanli Chang

Ryusuke Ushikoshi

David Cashman

Ronald R Stevens

Alexander S Polyak

Triet M Nguyen

Josef Thomas Hoog

Lei Jing

James Omer L'Heureux

Jeffrey Tyhach

Bruce B Pederson

Calvin R Augason

Eli Vronsky

Harold H Mortensen

Gabriel Ormonde

Quyen Doan

Jed Hsu

Juergen Henrich

Jianming Huang

Susanne Schlaefer

W N(Nick) Taylor

Taylor Nguyen

Allen Altwood

Rick Blum

Ramakanth Alapati

Ken Sautter

A batch processing oven includes a processing chamber, a magnet, and a rack. The processing chamber includes a gas inlet on a first side and a gas outlet on a second side opposite the first side, the gas inlet is configured to direct a hot gas into the processing chamber and the gas outlet is configured to exhaust the convective energy in parallel with the radiative energy from the walls. The magnet is arranged such that its north pole will be formed on the first side of the processing chamber and its south pole will be formed on the second side of the processing chamber. The rack is configured to be positioned between the first and second ends of the processing chamber and is configured to support a plurality of vertically spaced-apart substrates.

Batch processing oven for magnetic anneal

A method of improving interfacial adhesion of a copper-glass interface in a Through Glass Via (TGV) of an electronic device includes coating an internal wall of a TGV with a curable polymer material having a viscosity less than 30 Poise. The coating is cured to form a dielectric liner having a tensile strength greater than about 8 Mpa and a dielectric loss less than about 0.002. A layer of copper may then be deposited on the dielectric liner.

Dielectric liners on through glass vias

A solder reflow oven includes a processing chamber that defines an enclosure. The enclosure includes a spindle configured to support a substrate and rotate the substrate about a central axis of the processing chamber. The spindle is also configured to move vertically along the central axis and position the substrate at different locations within the enclosure. The oven further includes a chemical delivery tube configured to direct a chemical vapor into the enclosure, a lamp assembly configured to heat a top surface of the substrate, and a lift assembly configured to move the spindle along the central axis.

Processing oven

Systems and methods are provided for distributing clocks or other signals on an integrated circuit. In some aspects, one or more distributed deskewing objects are provisioned for reducing or eliminating skew while linking multiple clock distribution segments into one clock tree of an arbitrary shape and size.

Clock grid for integrated circuit

Systems and methods are provided for distributing clocks or other signals on an integrated circuit. In some aspects, one ore more distributed deskewing objects are provisioned for reducing or eliminating skew while linking multiple clock distribution segments into one clock tree of an arbitrary shape and size.

There is described apparatus and methods for transporting and processing substrates including wafers as to efficiently produce at reasonable costs improved throughput as compared to systems in use today. A linear transport chamber includes linear tracks and robot arms riding on the linear tracks to linearly transfer substrates along the sides of processing chambers for feeding substrates into a controlled atmosphere through a load lock and then along a transport chamber as a way of reaching processing chambers.

Apparatus and methods for transporting and processing substrates

Integrated circuits are provided with circuitry such as multiplexers that can be selectively configured to route different power supply voltages to different circuit blocks on the integrated circuits. The circuit blocks may contain memory elements that are powered by the power supply voltages and that provide corresponding static output control signals at magnitudes that are determined by the power supply voltages. The control signals from the memory elements may be applied to the gates of transistors in the circuit blocks. Logic on an integrated circuit may be powered at a given power supply voltage level. The memory elements may provide their output signals at overdrive voltage levels that are elevated with respect to the given power supply voltage level during high speed operation and may provide their output signals at relatively lower voltage levels that are less than the overdrive voltage during low power operation.

Integrated circuits with programmable overdrive capabilities

Integrated circuits with backside power delivery capabilities are provided. An integrated circuit may include a substrate having front and back surfaces, a first interconnect stack formed on the front surface, and a second interconnect stack formed on the back surface. Routing structures that carry data signals, control signals, and other user signals may be formed only in the first interconnect stack. A large majority of routing structures that carry power supply signals may be formed in the second interconnect stack. Decoupling capacitor circuitry such as deep trench capacitors may be formed in the back surface of the substrate. The integrated circuit may be mounted on a package substrate. The first interconnect stack may be coupled to the package substrate via wire bond pads, whereas the second interconnect stack may be coupled to the package substrate via an array of solder bumps.

Integrated circuits with backside power delivery

An integrated circuit is disclosed. The integrated circuit may include an interface circuit region and logic circuitry region. The interface circuit region includes interface circuits that transfers signals in and out of the integrated circuit. The logic circuitry region includes logic circuitry that is configured to implement a logic function. The logic circuitry region surrounds the interface circuit region from at least two sides, from at least three sides, or from all four sides.

Integrated circuit floorplans

In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

PLD architecture for flexible placement of IP function blocks

Methods and apparatus for transferring one or more substrates from a first pressure environment to a second pressure environment is provided. In one embodiment, a load lock chamber is provided. The load lock chamber comprises a first circular housing, and a second circular housing disposed within and movable relative to the first circular housing, one of the first circular housing or the second circular housing comprising a plurality of discrete regions, wherein at least a portion of the plurality of discrete regions are in selective fluid communication with one of at least two vacuum pumps based on the angular position of the second circular housing relative to the first circular housing.

Load lock chamber designs for high-throughput processing system

Techniques and mechanisms for providing embedded Input/Output (IO) blocks in a floor plan of a semiconductor device are provided, where the embedded IO blocks constitute partial columns (i.e., they do not extend from the bottom through to the top of the semiconductor device). In some embodiments, the partial column IO banks are skewed away from one another. In some embodiments, the partial column IO banks are located away from the center of the semiconductor device. Techniques and mechanisms for implementing symmetrical package routing using skewed partial column IO banks are also provided.

Skewed partial column input/output floorplan

A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.

Apparatus and methods for power management in integrated circuits

Growing community of inventors

Campbell, CA, United States of America

Christopher F Lane