At&t Bell Laboratories

Christopher Edmonds

James M Grinn

David J Brahm

Don R Draper

In a processor system having a central processor and secondary support processor mounted on a backplane board, a separate peripheral interrupt bus is provided for each secondary support processor to give full interrupt priority capability to peripheral devices connected to the support processors. The support processors (110, 120) and certain of the system's peripheral interface circuits (102, 104) are connected to the system's central processor (101) via a primary interrupt bus (105) and other peripheral interface circuits (112, 114, 122) are connected to their associated secondary processors (110, 120) via separate interrupt buses (115, 125) all on the same backplane board. The backplane board is divided into an upper section and a lower section and the primary interrupt bus and the interrupt request and acknowledge terminal pins for all circuit boards are in the lower section. The secondary processor boards and interface circuit boards served by the central processor have interrupt request and acknowledge terminal pins connected to the primary interrupt bus in the lower section. The interrupt request and acknowledge terminal pins for any peripheral interface circuit served by a secondary processor are connected to the associated secondary processor via a secondary interrupt bus formed in the upper section of the backplane and conductors extending between the sections.

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Batavia, IL, United States of America

Christopher Edmonds