Intel Corporation

Christopher E Yunker

Christopher P Mozak

Bryan L Spry

Theodore Zale Schoenborn

John V Lovelace

Kevin B Moore

Zvika Greenfield

Bruce Querbach

David G Ellis

Zale Theodore Schoenborn

Jay Joseph Nejedlo

Philip Abraham

Jayasekhar Tholiyil

Rony Ghattas

Charles D Lucas

Described herein is an apparatus for dynamically adjusting a voltage reference level for optimizing an I/O system to achieve a certain performance metric. The apparatus comprises: a voltage reference generator to generate a voltage reference; and a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event. The apparatus is used to perform the method comprising: generating a voltage reference for an input/output (I/O) system; determining a worst case voltage level of the voltage reference; dynamically adjusting, via a dynamic voltage reference control unit, the voltage reference level based on determining the worst case voltage level; and computing a center of an asymmetrical eye based on the dynamically adjusted voltage reference level.

Method and apparatus for dynamically adjusting voltage reference to optimize an I/O system

REUT (Robust Electrical Unified Testing) for memory links is introduced which speeds testing, tool development, and debug. In addition it provides training hooks that have enough performance to be used by BIOS to train parameters and conditions that have not been possible with past implementations. Address pattern generation circuitry is also disclosed.

Robust memory link testing using memory controller

In an embodiment, the effect of signal phase difference on a memory system is tested for various operating states. The various operating states may be represented as respective sample points on a plane defined by a range of values for a difference in signal phases and a range of values for another operating state parameter. In various embodiments, sample points for a round of crosstalk testing may include two sample points which are offset from the same reference point on the plane along different respective axes, where the axes are oblique to one another.

Method and system for evaluating effects of signal phase difference on a memory system

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Beaverton, OR, United States of America

Christopher E Yunker