National Semiconductor Corporation

Crosspoint Solutions, LLC

Chameleon Systems, Inc.

Element Cxi, LLC

Other

Intel Corporation

Christopher E Phillips

Laurence H Cooke

Dale Wong

Laurence Hager Cooke

Michael G Ahrens

Joseph G Nolan, Iii

John L Watson

Steven Hennick Kelem

Brian A Box

Robert Thomas Plunkett

Stephen L Wasson

William J Allen

Jaime C Cummins

Enno Wein

Charles A Furciniti

Shaila Hanrahan

Narendra Sankar

Mario D Nemirovsky

Robert James Divivier

Karl W Pfalzer

The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. In response to detection of a fault or failure, the state machine element re-assigns the first configuration to another composite circuit element and creates a second data link for performance of the same function. The assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation.

Fault tolerant integrated circuit architecture

Resilient integrated circuit architecture

The present invention, generally speaking, provides a hierarchy of configuration storage. The highest level of the hierarchy is an active configuration store; the lowest level is an off-chip configuration store; in between are one or more levels of configuration stores. Every configuration is promoted from the lowest off-chip level, through each level, up to the highest active level. Each ascending level of the hierarchy has a decreasing latency time required to promote a configuration to the next higher level of the hierarchy, and a decreasing amount of available storage. This separation into levels allows the amount of available storage to be adjusted depending on the inherent latency of the level's storage mechanism, where a longer latency requires a larger cache. This in turn allows the total required storage for a given performance level to be minimized.

Hierarchical storage architecture for reconfigurable logic configurations

A computer implemented method for automatically compiling a computer program written in a high level programming language into an intermediate data structure. The data structure is analyzed to identify critical blocks of logic, which can be implemented as an application specific integrated circuit (ASIC), to improve overall performance. The critical blocks of logic are transformed into new equivalent logic with maximal data parallelism. The parallelized logic is then translated into a Boolean gate representation, which is suitable for implementation on an ASIC. The ASIC may be coupled with a generic microprocessor via custom instruction for the microprocessor. The original computer program is then compiled into object code with the new expanded target instruction set.

Method for compiling high level programming languages into embedded microprocessor with multiple reconfigurable logic

An integrated circuit which contains a processor, and configurable logic with configuration memory such that the configurable logic can emulate a large memory array when the contents of the array are very sparse. This structure allows for fast access and a continuous updating capability while remaining internal to the chip. A methodology for recompressing the contents of the configurable logic while updating the configurable logic is also described.

Reconfigurable logic for table lookup

A reconfigurable system is arranged to have separate control and the data paths. The control path is set up using control fabric units which use an associated state machine to produce an address to a functional unit memory. The functional unit memory then produces the configuration data for the functional units. The use of a state machine allows for a very dense, highly-sequencable control unit that provides an encoded state to a memory which then allows a high number of control terms which results in a more linear interconnection to the data path units.

Control fabric unit including associated configuration memory and PSOP state machine adapted to provide configuration address to reconfigurable functional unit

A reconfigurable programmable sum of products generator allows for multiple configurations to be associated with a programmable sum of products generator. These configurations can be modified by changing the configurations in an associated configuration memory for the programmable sum of products generator. By using a reconfigurable programmable sum of products generator structure, a dense and highly interconnected logic is produced. Such a dense and highly interconnected logic is particularly valuable for use in the control path of a reconfigurable system.

Reconfigurable program sum of products generator

A system and method of logic synthesis uses a behavioral synthesis tool to convert a behavioral language description (e.g., behavioral description code, an intuitive algorithm, or programming language description) of an ASIC into a partitioned RTL language description including RTL sub-descriptions corresponding to each of control, datapath, and memory. Each of the higher level RTL sub-descriptions is then mapped directly (i.e., a one-to-one mapping correspondence) to re-configurable silicon structures without requiring an RTL synthesis tool to translate the RTL description into individual standardized cell logic gates and interconnect level description. The silicon structures are controlled by the RTL sub-descriptions to provide a direct synthesized physical implementation of the ASIC thereby providing a single step synthesis method of going from a behavioral description to a synthesized silicon implementation.

Behavioral silicon construct architecture and mapping

A configuration state memory is associated with a configurable functional block on a reconfigurable chip. The configuration state memory stores more than one configuration for the functional block. This allows the functional block to switch configurations without requiring the configuration data to be loaded from off-chip which would stall the operation of the reconfigurable chip. In a preferred embodiment, the configuration state memory uses a relatively few address bits to produce a relatively broad configuration output to the functional blocks. The small number of input address bits allows the configuration state memory to be addressed by relatively small state machine unit.

Configuration state memory for functional blocks on a reconfigurable chip

The present invention, generally speaking, provides a reconfigurable computing solution that offers the flexibility of software development and the performance of dedicated hardware solutions. A reconfigurable processor chip includes a standard processor, blocks of reconfigurable logic (,), and interfaces (,) between these elements. The chip allows application code to be recompiled into a combination of software and reloadable hardware blocks using corresponding software tools. A mixture of arithmetic cells and logic cells allows for higher effective utilization of silicon than a standard interconnect. More efficient use of configuration stack memory results, since different sections of converted code require different portions of ALU functions and bus interconnect. Many types of interfaces with the embedded processor are provided, allowing for fast interface between standard processor code and configurable &ldquo;hard-wired&rdquo; functions.

Integrated processor and programmable data path chip for reconfigurable computing

A pipelined processor in which the decoder can consume a portion of an instruction and hold that portion in sub-field shadow registers while retrieving the remainder of the instruction in a subsequent cycle or cycles. Each byte in a prefetch buffer is individually tagged such that the decoder can clear individual bytes in the prefetch buffer in order to allow additional instruction bytes to be prefetched before the current instruction is completely consumed and decoded by the decode stage. This allows for an optimal buffer size that is less than the maximum possible instruction length but large enough to hold a complete copy of the vast majority of instructions.

Tagged prefetch and instruction decoder for variable length instruction set and method of operation

A reconfigurable processor chip has a mixture of reconfigurable arithmetic cells and logic cells for higher effective utilization than a standard FPGA. The reconfigurable processor includes a standard microprocessor such as an embedded RISC processor. Many different types of interfaces are used to interface between the embedded processor and the reconfigurable portions of the chip, thus allowing for the fastest interface between standard processor code and configurable 'hard-wired' functions. A configuration memory stack is provided, allowing for nearly instantaneous reconfiguration. if desired, configuration planes can be shared between ALU function configuration and bus interconnect configuration, allowing more efficient use of stack memory.

Integrated processor and programmable data path chip for reconfigurable

A method is presented for automatically compiling a high level computer program down into an application specific integrated circuit coupled with a generic microprocessor. The original source code is written in a standard programming language such as ANSI C. Source code analysis is performed by our compiler to automatically determine which blocks of logic are most appropriate for the application specific integrated circuit and which for the generic microprocessor. The complete layout of the application specific integrated circuit is automatically generated by our compiler. Object code for the microprocessor, with custom instructions to invoke the application specific integrated circuit, is also automatically generated by our compiler.

Method for compiling high level programming languages into an integrated

A field programmable gate array integrated circuit which has numerous features for testing prior to programming the antifuses in the integrated circuit is provided. The circuits used to program the antifuses are also used for much of the preprogramming testing. The functionality of continuous series transistors and latch logic blocks may be tested together with the continuity of their programmable connections. Programmable input/output buffer circuits and clock circuits which set the desired clock network paths may be tested with signals on a serial scan path which passes through the input/output buffer circuits and clock circuits. Process characterization tests without the requirement of high-speed test equipment are also provided.

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San Jose, CA, United States of America

Christopher E Phillips