Intel Corporation

Sony Group Corporation

Christopher E Cox

Kuljit Singh Bains

Bill Nale

Christopher P Mozak

George Vergis

James A McCall

John R Goles

John B Halbert

Uksong Kang

Joydeep Ray

Arvind A Kumar

Xiang Li

Jaejin Lee

Navneet Dour

Ishmael F Santos

Jun Liao

Dean-Dexter R Eugenio

Rebecca Z Loop

Corinne Hall

Saher Abu Rahme

Pete D Vogt

Lakshminarayana Pappu

Howard S David

Tonia G Morris

Nadav Bonen

Nagi Aboulenein

Suneeta Sah

Chong J Zhao

Alexey Kostinsky

Hany M Fahmy

Hsien-Pao Yang

Robert J Friar

Akshith Vasanth

Yan Fu

David Wyatt

Justin J Song

Asaf Rubinstein

Israel Diamand

Xiuting C Man

Lawrence A Cooper

Hideo Oie

A memory device includes a grounded molding. The memory device includes a substrate having a first surface for a memory die, where the substrate has ground vias through substrate to connect to a ground reference. The substrate has a ball grid array (BGA) on the opposite surface, including perimeter balls to connect to ground connections. The grounded molding includes an electrically conductive epoxy mold to cover the memory die, where the electrical conductivity of the molding, with the molding grounded can provide radio frequency interference (RFI) shielding.

Memory device package with noise shielding

A system provides a mailbox communication register for communication between a host and a mode register. The mode register is to store configuration information, and write of configuration information to the mode register by the host takes less time than a read of the configuration information from the mode register by the host. The communication register is separate from the mode register and provides a location to store the configuration information for a read by the host. In response to a read request by the host, the mode register can copy the configuration information to the communication register and allow the host to read the register based on different timing rules than those that apply to the mode register. Instead of reading directly from a register that has timing variance between read and write, the host can read from a communication register.

Reading from a mode register having different read and write timing

A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.

Refresh command control for host assist of row hammer mitigation

A memory device is described. The memory device includes logic circuitry to perform calibrations of resistive network terminations and data drivers of the memory device while the memory device is within a self refresh mode.

Periodic calibrations during memory device self refresh

An apparatus is described. The apparatus includes a memory controller having an interface to communicate with a memory. The memory controller comprising logic circuitry to specify one of multiple possible write values to the memory during a write operation with multiple bits of a command that is sent on a command address bus that emanates from the interface. The memory to write any one of the possible write values into its storage cells while the memory interface is in a power saving state wherein the specified one write value is not articulated by the memory controller on a data bus of the interface as part of the write operation.

Memory command that specifies one of multiple possible write data values where the write data is not transported over a memory data bus

In a memory system an interface circuit includes an interface to a memory array, and to a data signal. The circuit includes loopback circuitry to enable loopback of received data signals without having to access the data from the memory array. The circuit can be part of a memory device, a register device, or a data buffer. The circuit interfaces to a memory array of a memory device, and performs loopback functions for a host controller that can test the operation of the interface.

Input/output (I/O) loopback function for I/O signaling testing

A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.

Applying chip select for memory device identification and power management control

A cache controller with a pattern recognition mechanism can identify patterns in cache lines. Instead of transmitting the entire data of the cache line to a destination device, the cache controller can generate a meta signal to represent the identified bit pattern. The cache controller transmits the meta signal to the destination in place of at least part of the cache line.

Representing a cache line bit pattern via meta signaling

A method is described. The method includes configuring first register space to establish ODT values of a data strobe signal trace of a DDR data bus. The method also includes configuring second register space to establish ODT values of a data signal trace of the DDR data bus. The ODT values for the data strobe signal trace are different than the ODT values for the data signal trace. The ODT values for the data strobe signal do not change when consecutive write operations of the DDR bus write to different ranks of a same DIMM.

DDR memory bus with a reduced data strobe signal preamble timespan

A chip select training mode (CSTM) enables a memory subsystem to train a chip select signal separately from command bus training. A memory device and a memory controller can connect via a command bus including a chip select signal line. Instead of training the chip select along with other signal lines of the command bus, a CSTM mode enables the memory subsystem to more accurately train the chip select. The memory device can be triggered for CSTM mode with a command, and then train voltage margining for the CS signal line to align chip select signaling with the memory subsystem clock signal.

Efficiently training memory device chip select control

In a computer system, a multilevel memory includes a near memory device and a far memory device, which are byte addressable. The multilevel memory includes a controller that receives a data request including original tag information. The controller includes routing hardware to selectively provide alternate tag information for the data request to cause a cache hit or a cache miss to selectively direct the request to the near memory device or to the far memory device, respectively. The controller can include selection circuitry to select between the original tag information and the alternate tag information to control where the data request is sent.

Dynamically programmable memory test traffic router

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Placerville, CA, United States of America

Christopher E Cox