Texas Instruments Corporation

Christopher Daniel Manack

Nazila Dadvand

Salvatore Frank Pavone

Patrick Francis Thompson

Vivek Swaminathan Sridharan

Sreenivasan Kalyani Koduri

Michael Todd Wyant

Joseph O Liu

Matthew John Sherbin

Qiao Chen

Rajen Manicon Murugan

Yiqi Tang

Siva Prakash Gurrum

Stefan Herzer

You Chye How

Liang Wan

Amit Sureshkumar Nangia

Hiep Xuan Nguyen

Frank Stepniak

Jonathan Andrew Montoya

Rakshit Agrawal

Steven Alfred Kummerl

Matthew David Romig

Leslie Edward Stark

Rafael Jose Lizares Guevara

Genki Yano

Shoichi Iriguchi

Hiroyuki Sada

Jovenic Romero Esquejo

Maricel Fabia Escaño

Bradley Andrew Glasscock

Madison Paige Koziol

Keith Edward Johnson

Ming Zhu

In examples, a chip scale package (CSP) comprises a semiconductor die; a conductive terminal coupled to the semiconductor die; and a non-conductive coat covering a backside of the semiconductor die and a sidewall of the semiconductor die. The non-conductive coat has a thickness of less than 45 microns.

Coated semiconductor dies

A method includes performing a laser ablation process that removes a portion of a wafer to form a trench in a scribe region between adjacent die regions of the wafer, the trench extending from a first side of the wafer toward an opposite second side of the wafer, the trench extending through a metallization structure and an active circuit portion of the wafer, and a bottom of the trench spaced apart from the second side of the wafer. The method also includes performing a wafer expansion process that separates individual semiconductor dies from the wafer after the laser ablation process.

Laser ablation for die separation to reduce laser splash and electronic device

In some examples, a method for manufacturing a semiconductor package comprises coupling a photoresist layer to a non-device side of a semiconductor wafer, the semiconductor wafer having a device side, first and second circuits formed in the device side and separated by a scribe street, a test device positioned in the scribe street. The method also comprises coupling a tape to the device side of the semiconductor wafer. The method also comprises performing a photolithographic process to form an opening in the photoresist layer and plasma etching through the semiconductor wafer by way of the opening in the photoresist layer to produce first and second semiconductor dies having the first and second circuits, respectively. The method also comprises removing the tape from device sides of the first and second semiconductor dies, wherein removing the tape includes removing the test device. The method also comprises coupling the first circuit of the first semiconductor die to a conductive member. The method also comprises covering the first semiconductor die with a mold compound, the conductive member exposed to an exterior surface of the mold compound.

Efficient removal of street test devices during wafer dicing

In examples, a semiconductor device comprises a semiconductor package including a mold compound covering a semiconductor die. The semiconductor package has a surface and a cavity formed in the surface. The semiconductor device comprises an electronic device positioned within the cavity, the electronic device coupled to the semiconductor die via a conductive terminal extending through the mold compound.

Electronic devices in semiconductor package cavities

Described examples provide microelectronic devices and fabrication methods, including fabricating a contact structure by forming a titanium or titanium tungsten barrier layer on a conductive feature, forming a tin seed layer on the barrier layer, forming a copper structure on the seed layer above the conductive feature of the wafer or die, heating the seed layer and the copper structure to form a bronze material between the barrier layer and the copper structure, removing the seed layer using an etching process that selectively removes an exposed portion of the seed layer, and removing an exposed portion of the barrier layer.

Contact with bronze material to mitigate undercut

In examples, a sensor package includes a semiconductor die, a sensor on the semiconductor die, and a ring encircling the sensor. The sensor and an inner surface of the ring are exposed to an exterior environment of the sensor package. The sensor package includes a mold compound covering the semiconductor die and abutting an outer surface of the ring.

Miniature sensor cavities

In some examples, a chip scale package (CSP) comprises a semiconductor die; a passivation layer abutting the semiconductor die; a via extending through the passivation layer; and a first metal layer abutting the via. The CSP also includes an insulation layer abutting the first metal layer, with the insulation layer having an orifice with a maximal horizontal area of less than 32400 microns. The CSP further includes a second metal layer abutting the insulation layer and adapted to couple to a solder ball. The second metal layer abuts the first metal layer at a point of contact defined by the orifice in the insulation layer.

Efficient redistribution layer topology

In examples, a semiconductor package comprises a semiconductor die having an active surface; a conductive layer coupled to the active surface; and a polyimide layer coupled to the conductive layer. The package also comprises a conductive pillar coupled to the conductive layer and to the polyimide layer; a flux adhesive material coupled to the conductive pillar; and a solder layer coupled to the flux adhesive material. The package further includes a conductive terminal coupled to the solder layer and exposed to a surface of the package, the active surface of the semiconductor die facing the conductive terminal.

Conductive members for die attach in flip chip packages

A microelectronic device is formed by thinning a substrate of the microelectronic device from a die attach surface of the substrate, and forming a copper-containing layer on the die attach surface of the substrate. A protective metal layer is formed on the copper-containing layer. Subsequently, the copper-containing layer is attached to a package member having a package die mount area. The protective metal layer may optionally be removed prior to attaching the copper-containing layer to the package member. Alternatively, the protective metal layer may be left on the copper-containing layer when the copper-containing layer is attached to the package member. A structure formed by the method is also disclosed.

Die attach surface copper layer with protective layer for microelectronic devices

Described examples include a process that includes forming a diffusion barrier layer on a backside of a semiconductor wafer. The process also includes forming a seed copper layer on the diffusion barrier layer. The process also includes forming a copper layer on the seed copper layer. The process also includes immersion plating a silver layer on the copper layer.

Plating for thermal management

In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions; at least one semiconductor device die over the die mount portion of the package substrate, the semiconductor device die having bond pads on an active surface facing away from the package substrate; electrical connections between at least one of the bond pads and one of the lead portions; a post interconnect over at least one of the bond pads, the post interconnect extending away from the active surface of the semiconductor device die; and a dielectric material covering a portion of the package substrate, the semiconductor device die, a portion of the post interconnect, and the electrical connections, forming a packaged semiconductor device, wherein the post interconnect extends through the dielectric material and had an end facing away from the semiconductor device die that is exposed from the dielectric material.

Three dimensional package for semiconductor devices and external components

An integrated circuit (IC) die includes a substrate with circuitry configured for at least one function including metal interconnect levels thereon including a top metal interconnect level and a bottom metal interconnect level, with a passivation layer on the top metal interconnect level. A scribe street is around a periphery of the IC die, the scribe street including a scribe seal utilizing at least two of the plurality of metal interconnect levels, an inner metal meander stop ring including at least the top metal interconnect level located outside the scribe seal, wherein the scribe seal and the inner metal meander stop ring are separated by a first separation gap. An outer metal meander stop ring including at least the top metal interconnect level is located outside the inner metal stop ring, wherein the outer stop ring and the inner stop ring are separated by a second separation gap.

Integrated circuit with metal stop ring outside the scribe seal

A method for manufacturing a package includes positioning a copper layer above a die. A zinc layer is positioned on the copper layer. The zinc and copper layers are then heated to produce a brass layer, the brass layer abutting the copper layer. Further, a polymer layer is positioned abutting the brass layer.

Method of forming brass-coated metals in flip-chip redistribution layers

A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.

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Flower Mound, TX, United States of America

Christopher Daniel Manack