Google Inc.

Christopher Daniel Leary

Rahul Nagarajan

Dong Hyuk Woo

Ravi Narayanaswami

Thomas James Norrie

Thejasvi Magudilu Vijayaraj

Jingyue Wu

Hema Hariharan

Arpith Chacko Jacob

Suvinay Subramanian

Robert Coleman Springer, Iv

Aspects of the disclosure are directed to methods, systems, and apparatuses using an instruction prefetch pipeline architecture that provides good performance without the complexity of a full cache coherent solution deployed in conventional CPUs. The architecture can include components which can be used to construct an instruction prefetch pipeline, including instruction memory (TiMem), instruction buffer (iBuf), a prefetch unit, and an instruction router.

Cooperative instruction prefetch on multicore system

Methods, systems, and apparatus, including computer programs encoded on computer storage media for performing logic equivalence check on a circuit design are described. In one aspect, a method includes receiving a request for performing operations of a logical equivalence check of a circuit design and determining, based on one or more criteria, to perform the operations using pipeline stages. In response to the determination, a plurality of pipeline stages of the circuit design that is in a high level representation are determined. For each stage of the plurality of pipeline stages, data corresponding to a high level representation of the stage are obtained, and data corresponding to a low level representation of the stage that corresponds to the high level representation of the stage are obtained. The high level representation and the low level representation are compared. An output is generated based on the comparison.

Logical equivalence check for circuits

Aspects of the disclosure provide for an accelerator capable of accelerating data dependent, irregular, and/or memory-bound operations. An accelerator as described herein includes a programmable engine for efficiently executing computations on-chip that are dynamic, irregular, and/or memory-bound, in conjunction with a co-processor configured to accelerate operations that are predictable in computational load and behavior on the co-processor during design and fabrication.

Programmable accelerator for data-dependent, irregular operations

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for generating a data entity that causes a processing unit to process a computational graph. In one aspect, a method includes the actions of receiving data identifying a computational graph, the computational graph including a plurality of nodes representing operations; obtaining compilation artifacts for processing the computational graph on a processing unit; and generating a data entity from the compilation artifacts, wherein the data entity, when invoked, causes the processing unit to process the computational graph by executing the operations represented by the plurality of nodes.

Executing computational graphs on graphics processing units

Methods, systems, and apparatus, including a system for transforming sparse elements to a dense matrix. The system is configured to receive a request for an output matrix based on sparse elements including sparse elements associated with a first dense matrix and sparse elements associated with a second dense matrix; obtain the sparse elements associated with the first dense matrix fetched by a first group of sparse element access units; obtain the sparse elements associated with the second dense matrix fetched by a second group of sparse element access units; and transform the sparse elements associated with the first dense matrix and the sparse elements associated with the second dense matrix to generate the output dense matrix that includes the sparse elements associated with the first dense matrix and the sparse elements associated with the second dense matrix.

Matrix processing apparatus

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for generating a data entity that causes a processing unit to process a computational graph. In one aspect, method includes the actions of receiving data identifying a computational graph, the computational graph including a plurality of nodes representing operations; obtaining compilation artifacts for processing the computational graph on a processing unit; and generating a data entity from the compilation artifacts, wherein the data entity, when invoked, causes the processing unit to process the computational graph by executing the operations represented by the plurality of nodes.

Methods, systems, and apparatus, including a system for transforming sparse elements into a dense matrix. The system includes a data fetch unit that includes a plurality of processors, the data fetch unit configured to determine, based on identifications of the subset of the particular sparse elements, a processor designation for fetching the subset of the particular sparse elements. The system includes a concatenation unit configured to generate an output dense matrix based on a transformation that is applied to the sparse elements fetched by the data fetch unit.

Growing community of inventors

Mountain View, CA, United States of America

Christopher Daniel Leary